VLSI Technology LLC v. Intel Corporation, No. 5:2017cv05671 - Document 778 (N.D. Cal. 2023)

Court Description: ORDER GRANTING IN PART AND DENYING IN PART VLSI'S MOTION FOR SUMMARY JUDGMENT; GRANTING IN PART AND DENYING IN PART INTEL'S MOTION FOR SUMMARY JUDGMENT (public redacted version of sealed order filed at 772 ). Signed by Judge Beth Labson Freeman on 12/7/2023. (blflc3, COURT STAFF) (Filed on 12/14/2023)

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VLSI Technology LLC v. Intel Corporation Doc. 778 1 2 3 UNITED STATES DISTRICT COURT 4 NORTHERN DISTRICT OF CALIFORNIA 5 SAN JOSE DIVISION 6 7 VLSI TECHNOLOGY LLC, Plaintiff, 8 United States District Court Northern District of California 9 v. 10 INTEL CORPORATION, 11 Defendant. 12 Case No. 17-cv-05671-BLF ORDER GRANTING IN PART AND DENYING IN PART VLSI’S MOTION FOR SUMMARY JUDGMENT; GRANTING IN PART AND DENYING IN PART INTEL’S MOTION FOR SUMMARY JUDGMENT [Re: ECF Nos. 580, 586] 13 14 Plaintiff VLSI Technology LLC (“VLSI”) brought the instant patent infringement action 15 against Defendant Intel Corporation (“Intel”). At issue are four patents: U.S. Patent No. 8,566,836 16 (“’836 Patent”), U.S. Patent No. 8,004,922 (“’922 Patent”), U.S. Patent No. 7,675,806 (“’806 17 Patent”), and U.S. Patent No. 8,268,672 (“’672 Patent”) (collectively the “Asserted Patents”). 18 VLSI accuses various Intel technologies and processes of infringing the Asserted Patents. 19 Before the Court are the parties’ Motions for Summary Judgment. VLSI seeks summary 20 judgment (1) in VLSI’s favor on Intel’s affirmative defense that it is licensed to use all asserted 21 patents and (2) of no invalidity based on six prior art combinations under IPR estoppel. ECF No. 22 586 (“VLSI Mot.”) at 1, 15–16; ECF No. 735 (“VLSI Reply”). Intel opposes the motion. ECF 23 No. 672 (“Intel Opp.”). Intel seeks summary judgment (1) of no infringement of the ’836 Patent, 24 (2) of no infringement of the ’922 Patent, (3) of invalidity of the asserted claims for the ’922 25 Patent, (4) of no infringement of the ’806 Patent, (5) of no infringement of the ’672 Patent, (6) that 26 it is licensed to use the Asserted Patents, and (7) of no willful infringement, no indirect 27 infringement, and no enhanced damages for any patent. ECF No. 580 (“Intel Mot.”) at 1; ECF 28 No. 710 (“Intel Reply”). VLSI opposes the motion. ECF No. 677 (“VLSI Opp.”). Dockets.Justia.com After careful consideration, VLSI’s Motion for Summary Judgment is GRANTED IN 1 2 PART and DENIED IN PART and Intel’s Motion for Summary Judgment is GRANTED IN 3 PART and DENIED IN PART. 4 5 I. BACKGROUND The ’836 Patent, entitled “Multi-Core System on Chip,” claims a multi-core chip “in 6 United States District Court Northern District of California ’836 Patent A. 7 which a speed information for each core, such as the maximum operation speed” is extracted and 8 stored, then “may be accessed and used by the operating system when allocating workload among 9 the cores by selecting the fasted [sic] core to run any applications or tasks that can not be executed 10 on a plurality of cores.” ’836 Patent at Abstract (cleaned up). More succinctly, when a single- 11 core task is given to a multi-core processor, the processor gives that task to the fastest core. See 12 id. at 2:1–13. VLSI accuses Intel of infringing claims 1, 9–11, 13, 17, 20, and 21 of the ’836 Patent. 13 14 Each asserted claim requires, among other things, that “upon identifying” a task as a single-core 15 task, the fastest core in the processor is “select[ed]” (claims 1, 9–11, 13, 17) or “identified” 16 (claims 20, 21) to run that single-core task. ECF No. 241 (“Markman Order”) 22–25 (construing 17 claim 10 to include the same “upon identifying” limitation as claims 1 and 20). 18 19 ’922 Patent B. The ’922 Patent, entitled “Power Island with Independent Power Characteristics for 20 Memory and Logic,” claims a power island with two segments, a first segment that “includes a 21 hardware device and operates the hardware device at first power characteristics” and second 22 segment that “includes scalable logic and operates the scalable logic at second power 23 characteristics” such that the first and second power characteristics “are different.” ’922 Patent at 24 Abstract. 25 VLSI accuses Intel of infringing claims 4, 5, and 18 of the ’922 Patent. The Asserted 26 Claims of the ’922 Patent require certain components within the “power island” to have “power 27 characteristics” that are “different” (claims 4 and 5) or “partially different” (claim 18) from the 28 “power characteristics” of other components within the “power island.” ’922 Patent at 9:15–20, 2 1 12:6–13. The Asserted Claims also require a “supply power converter” that converts “external 2 supply signal (VDD)” (’922 Patent at 9:27–37, 12:1–13) and a “reference power converter” that 3 converts “reference signal (VSS)” (’922 Patent at 9:50–61, 12:23–28). 4 The ’806 Patent, entitled “Low Voltage Memory Device and Method Thereof,” claims two 5 United States District Court Northern District of California ’806 Patent C. 6 memories, a “first memory” and a “second memory,” both of which are located in an integrated 7 circuit. ’806 Patent at Abstract. “The first memory is a relatively high-density memory device, 8 capable of storing large amounts of data relative to the second memory” and the “second memory 9 is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage 10 at which the first memory can be accessed.” Id. The circuit is thus “able to store large amounts of 11 data in the high density memory in a normal or active mode of operation, and also have access to 12 the low-voltage memory during the low-voltage mode of operation.” Id. VLSI accuses Intel of infringing claims 11, 12, 13, and 15 of the ’806 Patent. The 13 14 Asserted Claims require a “first memory” and a “second memory,” and two different modes of 15 operation: “a first mode of operation” and “a second mode of operation.” ’806 Patent at 10:31–57. 16 The Court construed “second mode of operation” to require that, “when in the second mode of 17 operation, both the voltage provided to the first memory and the voltage provided to the second 18 memory must be lower than the minimum operating voltage of the first memory.” Markman 19 Order at 7. 20 21 D. ’672 Patent The ’672 Patent, entitled “Method of Assembly and Assembly Thus Made,” claims an 22 assembly “comprising a first chip and a second chip which are interconnected through solder 23 connections” that “comprise, at the first chip, an underbump metallization and a solder bump, and, 24 at the second chip, a metallization” such that “the solder bump is provided as a fluid layer with a 25 contact angle of less than 90°.” ’672 Patent at Abstract. 26 VLSI accuses Intel of infringing claim 2 of the ’672 Patent. Claim 2 is directed to “[a] 27 method of assembly of a first chip to a second chip” that includes a series of steps, including (1) 28 “providing . . . a solder composition” to “a plurality of bond pads at a surface of the first chip . . . 3 1 with an underbump metallization,” “wherein the solder composition is provided as a fluid layer on 2 the underbump metallization,” and (2) further requiring that the solder composition “makes a 3 contact angle of less than 90° with the underbump metallization.” ’672 Patent at 8:2–22; 4 Markman Order at 19. United States District Court Northern District of California 5 E. License Agreement 6 In 2012, Intel entered into an agreement with certain Finjan entities and affiliates, whereby 7 Intel received a “perpetual, irrevocable license” to “Finjan’s Patents[.]” ECF No. 579-17 (“Finjan 8 License Agreement” or “Agreement”) § 3.1. The term “Finjan” expressly includes Finjan, Inc., 9 Finjan Software, Inc., and their “Affiliates.” Id. at Preamble. The term “Affiliates” is defined as 10 “any Person that, now or hereafter, directly or indirectly through one or more entities, controls or 11 is controlled by, or is under common control with, [a] specified Person.” Id. §1.2. Fortress 12 Investment Group (“Fortress”), the company that formed and controls VLSI, acquired control of 13 Finjan Holdings LLC (“FHL”) in 2020. Intel Mot. at 18. 14 VLSI and its parent company CF VLSI Holdings LLC (“VLSI Holdings”) were created in 15 2016 for the purpose of acquiring and licensing a portfolio of semiconductor patents from NXP 16 Semiconductors (“NXP”). VLSI Mot. at 2. VLSI and VLSI Holdings were capitalized by ten 17 different investment funds managed by Fortress, with the majority investor in VLSI Holdings 18 being Fortress Credit Opportunities Fund IV (“FCO IV”), which is a closed-end mutual fund with 19 hundreds of investors and $1.8 billion under management as of June 30, 2022. ECF No. 586-3 20 (“LLC Agreement”) at VLSI-18-966DE00050646; ECF No. 586-4 (“Stolarski Decl.”) ¶¶ 7, 10; 21 ECF No. 589-2 (Zur Dep.) 119:10–25; ECF No. 589-3 (James Dep.) 131:19–132:6; ECF No. 586- 22 7 (2022-07-11 Del. Stolarski Decl.) ¶ 5. VLSI is 100% owned by VLSI Holdings, which in turn is 23 owned by 10 different investment funds (with the majority owner being FCO IV), all of which are 24 managed by Fortress. LLC Agreement at VLSI-18-966DE00050646; Stolarski Decl. ¶ 10. 25 VLSI and NXP entered into a Patent Purchase and Cooperation Agreement (“PPCA”), by 26 which VLSI purchased a group of semiconductor patents that had been developed by NXP and its 27 predecessors, and NXP agreed to cooperate in VLSI’s assertion of the NXP patents against Intel 28 and others. In exchange, NXP received a large upfront payment from VLSI and is entitled to a 4 1 share of licensing profits that VLSI obtains on the NXP patents. Stolarski Decl. ¶ 4; ECF No. 2 586-9 (Stolarski Dep. 10/17/19) 227:24–228:20; ECF No. 586-10 (Stolarski Dep. 7/9/20) 146:12– 3 14, 148:22–149:3; ECF No. 586-11 (PPCA) at §§ 2.1, 7.3. 4 F. In October 2017, VLSI filed this action against Intel asserting several of the NXP patents. 5 United States District Court Northern District of California Procedural History and Parallel Litigation 6 ECF No. 1 (“Compl.”). VLSI subsequently filed a separate patent infringement action against 7 Intel on other NXP patents in the District of Delaware, as well as three more patent infringement 8 actions against Intel on NXP patents in the Western District of Texas. VLSI Mot. at 3. The later 9 four district court actions initiated by VLSI against Intel have already been largely resolved at the 10 trial court level: the first Western District of Texas case resulted in a $2.18 billion jury verdict and 11 subsequent judgment in favor of VLSI, which the Federal Circuit has recently reversed; the second 12 Western District of Texas case resulted in a defense verdict for Intel; the third Western District of 13 Texas case resulted in a $949 million jury verdict in favor of VLSI that is presently at the post- 14 trial motion stage; and the Delaware suit was dismissed on December 27, 2022 by mutual 15 agreement of the parties before any trial date had been set. Id. Intel first asserted its license defense against VLSI on September 2, 2020 in one of the 16 17 Western District of Texas actions (VLSI Technology LLC v. Intel Corporation, No. 6:21-CV-57- 18 ADA (W.D. Tex.)), and subsequently asserted the same license theory in the parties’ District of 19 Delaware action on September 11, 2020 (VLSI Technology LLC v. Intel Corporation, No. 18-cv- 20 966-CFC-CJB (D. Del.)), in Delaware Chancery Court on January 11, 2021, and finally in this 21 Court on December 15, 2021 (ECF No. 330-1 at 13). VLSI Mot. at 4. 22 23 II. LEGAL STANDARD Federal Rule of Civil Procedure 56 governs motions for summary judgment. Summary 24 judgment is appropriate if the evidence and all reasonable inferences in the light most favorable to 25 the nonmoving party “show that there is no genuine issue as to any material fact and that the 26 moving party is entitled to a judgment as a matter of law.” Celotex Corp. v. Catrett, 477 U.S. 317, 27 322 (1986). The current version of Rule 56 authorizes a court to grant “partial summary 28 judgment” to dispose of less than the entire case and even just portions of a claim or defense. See 5 1 Fed. R. Civ. Proc. advisory committee’s note, 2010 amendments; Ochoa v. McDonald’s Corp., 2 133 F.Supp.3d 1228, 1232 (N.D. Cal. 2015). United States District Court Northern District of California 3 The moving party “bears the burden of showing there is no material factual dispute,” Hill 4 v. R+L Carriers, Inc., 690 F.Supp.2d 1001, 1004 (N.D. Cal. 2010), by “identifying for the court 5 the portions of the materials on file that it believes demonstrate the absence of any genuine issue 6 of material fact.” T.W. Elec. Serv. Inc. v. Pac. Elec. Contractors Ass’n, 809 F.2d 626, 630 (9th 7 Cir. 1987). In judging evidence at the summary judgment stage, the Court “does not assess 8 credibility or weigh the evidence, but simply determines whether there is a genuine factual issue 9 for trial.” House v. Bell, 547 U.S. 518, 559–60 (2006). A fact is “material” if it “might affect the 10 outcome of the suit under the governing law,” and a dispute as to a material fact is “genuine” if 11 there is sufficient evidence for a reasonable trier of fact to decide in favor of the nonmoving party. 12 Anderson v. Liberty Lobby, Inc., 477 U.S. 242, 248 (1986). 13 Where the moving party will have the burden of proof on an issue at trial, it must 14 affirmatively demonstrate that no reasonable trier of fact could find other than for the moving 15 party. Celotex, 477 U.S. at 325; Soremekun v. Thrifty Payless, Inc., 509 F.3d 978, 984 (9th Cir. 16 2007). By contrast, where the moving party does not have the burden of proof on an issue at trial, 17 it “must either produce evidence negating an essential element of the nonmoving party’s claim or 18 defense or show that the nonmoving party does not have enough evidence of an essential element 19 to carry its ultimate burden of persuasion at trial.” Nissan Fire & Marine Ins. Co. v. Fritz 20 Companies, Inc., 210 F.3d 1099, 1102 (9th Cir. 2000). 21 Once the moving party meets its initial burden, the nonmoving party must set forth, by 22 affidavit or as otherwise provided in Rule 56, “specific facts showing that there is a genuine issue 23 for trial.” Liberty Lobby, 477 U.S. at 250 (internal quotation marks omitted). In determining 24 whether a genuine issue of material fact exists, “[t]he evidence of the non-movant is to be 25 believed, and all justifiable inferences are to be drawn in his favor.” Id. at 255 (citation omitted). 26 If the nonmoving party’s “evidence is merely colorable, or is not significantly probative, summary 27 judgment may be granted.” Id. at 249–50 (internal citations omitted). Mere conclusory, 28 speculative testimony in affidavits and moving papers is also insufficient to raise genuine issues of 6 1 fact and defeat summary judgment. See Thornhill Publ’g Co. v. GTE Corp., 594 F.2d 730, 738 2 (9th Cir. 1979). For a court to find that a genuine dispute of material fact exists, “there must be 3 enough doubt for a reasonable trier of fact to find for the [non-moving party].” Corales v. Bennett, 4 567 F.3d 554, 562 (9th Cir. 2009). 5 III. 6 7 United States District Court Northern District of California 8 DISCUSSION A. VLSI’s Motion 1. License Defense a. Res Judicata and Collateral Estoppel 9 VLSI had a strong argument that res judicata and collateral estoppel barred Intel’s license 10 defense until December 4, 2023 when the Federal Circuit reversed the Texas district court ruling 11 on which this argument was based. VLSI Technology LLC v. Intel Corporation, Case No. 22-1906 12 (Fed. Cir. Dec. 4, 2023). With this turn of events, VLSI’s motion on this ground is denied. 13 14 b. Merits of the License Defense VLSI seeks summary judgment that it is not bound by the Finjan License Agreement. 15 VLSI argues that it is not a party to the Agreement (VLSI Mot. at 7–12) and the Asserted Patents 16 are not “Finjan’s Patents” (id. at 12–15). The recency of the Federal Circuit’s decision requires 17 this Court to fully analyze the issues raised in the parties’ Motions for Summary Judgment, which 18 will require consideration of the Federal Circuit’s ruling. In the interest of providing the parties 19 with the bulk of its ruling on the motions without further delay, the Court will issue a 20 supplemental order addressing the merits of the license defense as soon as possible. 21 22 2. IPR Estoppel Next, VLSI seeks summary judgment of no invalidity based on six prior art combinations 23 discussed in Intel’s expert reports under the doctrine of IPR estoppel. Intel expert Dr. Alyssa B. 24 Apsel’s obviousness analysis concerns the’922 Patent, setting forth the following three 25 combinations of prior art references: 26 (1) The Nehalem Processor (“Nehalem” or “Nehalem Processor”), U.S. Patent No. 27 8,397,090 (“Gunther”), and U.S. Patent No. 7,723,867 (“Willingham”) (collectively, 28 “Nehalem, Gunther, and Willingham”) (ECF No. 588-7 (“Apsel Report”) ¶¶ 771–961); 7 United States District Court Northern District of California 1 (2) U.S. Patent No. 8,171,323 (“Rakshani”) and Willingham (collectively, “Rakshani and 2 Willingham”) (id. ¶¶ 962–1096); 3 (3) Rakshani and U.S. Patent No. 7,307,899 (“Khellah”) (collectively, “Rakshani and 4 Khellah”) (id. ¶¶ 1097–1132). 5 VLSI Mot. at 17. Intel expert Dr. Patrick Fay’s obviousness analysis concerns the ’672 Patent, 6 setting forth the following three combinations of prior art references: 7 (4) Japanese Patent Application JP-A 02-005455 (“Okada”), U.S. Patent No. 6,070,788 8 (“Zakel”), and the Lee Book (collectively, “Okada, Zakel, and the Lee Book”) (ECF No. 9 588-8 (“Fay Report”) ¶¶ 139–88); 10 (5) Okada, the Lee Book, and the Intel P1264 Package Process (“P1264 Process”) 11 (collectively, “Okada, the Lee Book, and the Intel P1264 Package Process”) (id. ¶¶ 189– 12 246); and 13 (6) Barbara Pahl et al., A Thermode Bonding Process for Fine Pitch Flip Chip Applications 14 Down to 40 Micron, 2001 Proceedings, Int’l Symp. on Elec. Materials & Packaging 15 (“Pahl”), U.S. Patent Application Publication No. 2002/0149117 (“Shibata”), and U.S. 16 Patent Application Publication No. 2004/0012090 (“Basol”) (collectively, “Pahl, Shibata, 17 and Basol”) (id. ¶¶ 247–86). 18 VLSI Mot. at 17. VLSI seeks summary judgment that Intel should be estopped from asserting 19 these six obviousness combinations. 20 A petitioner whose challenge to a patent claim in IPR results in a Final Written Decision 21 cannot later assert in litigation “that the claim is invalid on any ground that the petitioner . . . 22 reasonably could have raised during that inter partes review.” 35 U.S.C. § 315(e)(2). “[E]stoppel 23 applies not just to claims and grounds asserted in the petition and instituted for consideration by 24 the Board, but to all grounds not stated in the petition but which reasonably could have been 25 asserted against the claims included in the petition.” Click-to-Call Techs. LP v. Ingenio, Inc., 45 26 F.4th 1363, 1370 (Fed. Cir. 2022) (quoting California Inst. of Tech. v. Broadcom Ltd., 25 F.4th 27 976, 991 (Fed. Cir. 2022)). 28 VLSI makes three arguments. First VLSI argues that three of the combinations – (2) 8 1 Rakshani and Willingham; (3) Rakshani and Khellah; and (6) Pahl, Shibata, and Basol – are 2 barred because each of the references was disclosed before or as part of Intel’s IPR Petitions. 3 VLSI Mot. at 17–19. Second, VLSI argues that the combination (4) Okada, Zakel, and the Lee 4 Book is barred because it relies on the Lee Book. Id. at 19–20. Third, VLSI argues that two of the 5 combinations – (1) Nehalem, Gunther, and Willingham; and (5) Okada, the Lee Book, and the 6 Intel P1264 Package Process – are barred because they improperly rely on “product” prior art. Id. 7 at 20–25. 8 United States District Court Northern District of California 9 a. Prior Art Disclosed by June 2018 First, VLSI seeks summary judgment that IPR Estoppel bars Intel from three obviousness 10 combinations: (2) Rakshani and Willingham; (3) Rakshani and Khellah; and (6) Pahl, Shibata, 11 and Basol. VLSI lists several asserted prior art references Dr. Apsel and Dr. Fay rely on for their 12 Section 103 obviousness analyses that Intel disclosed in its March 19, 2018 Invalidity Contentions 13 and June 2018 IPR petitions. VLSI Mot. at 18. VLSI presents evidence that Intel disclosed 14 Rakshani and Basol in its March 19, 2018 Invalidity Contentions, which predate the ’922 and ’672 15 Petitions (see ECF No. 588-13 (“Invalidity Contentions”) at 38, 62). VLSI presents evidence that 16 Intel disclosed Willingham and Khellah in the ’922 Petition. See Petition for Inter Partes Review 17 of U.S. Patent No. 8,004,922 at 1, 3, 10 Intel Corp. v. VLSI Tech. LLC, No. IPR2018-01033 18 (P.T.A.B. June 21, 2018). And VLSI presents evidence that Intel disclosed Shibata and Pahl in its 19 ’672 Petition. Petition for Inter Partes Review of U.S. Patent No. 8,268,672 at 1, Intel Corp. v. 20 VLSI Tech. LLC, No. IPR2018-01107 (P.T.A.B. June 13, 2018). Thus, VLSI argues, the Court 21 should grant summary judgment of no invalidity as to combinations (2), (3), and (6) because 22 “[t]hese combinations consist entirely of references Intel explicitly disclosed as prior art at the 23 time it filed its IPR petitions, and are thus estopped under Section 315(e)(2).” VLSI Mot. at 18. 24 In response, Intel concedes that “the Federal Circuit has held that IPR estoppel attaches to 25 ‘all grounds . . . which reasonably could have been asserted against the claims included in the 26 petition.’” Intel Opp. at 24–25 (quoting Broadcom, 25 F.4th at 991). Intel states that it seeks to 27 preserve its position that IPR estoppel should not bar these prior art grounds because the plain text 28 of the estoppel statute provides that IPR estoppel applies to “any ground that the petitioner raised 9 1 or reasonably could have raised during that inter partes review,” 35 U.S.C. § 315(e)(2). 2 The Federal Circuit recently held in Broadcom that, where it is “undisputed” that a patent 3 challenger was “aware of the prior art references that [it] sought to raise in the district court when 4 [it] filed its IPR petitions,” “summary judgment . . . of no invalidity based on IPR estoppel” is 5 warranted. 25 F.4th at 991, 995. Although Intel wishes to preserve its argument that Broadcom 6 was wrongly decided, it acknowledges that this Court must follow Broadcom. As such, VLSI’s 7 Motion for Summary Judgment that IPR estoppel precludes Intel from relying on the three 8 obviousness combinations – (2) Rakshani and Willingham; (3) Rakshani and Khellah; and (6) 9 Pahl, Shibata, and Basol – is granted. 10 b. Okada, Zakel, and the Lee Book Second, VLSI seeks summary judgment that IPR Estoppel bars Intel from obviousness United States District Court Northern District of California 11 12 combination (4) Okada, Zakel, and the Lee Book because “Intel was aware of or reasonably could 13 have raised the Lee Book at the time it filed the ’672 Petition.” VLSI Mot. at 19–20. Intel responds that it does not rely on a combination of Okada, Zakel, and the Lee Book, 14 15 but instead Intel says that it has asserted “applicant admitted prior art (‘AAPA’)—i.e., admissions 16 regarding prior art contained in the ’672 Patent—in combination with the Lee Book.” Intel Opp. 17 at 23–24 (citing Fay Report ¶¶ 139–88). Intel notes that “VLSI does not move for summary 18 judgment based on that combination, and instead argues that ‘VLSI is entitled to summary 19 judgment of no invalidity concerning Intel’s combination of Okada, Zakel, and Lee Book.’” Mot. 20 20. The Court agrees with Intel. VLSI’s motion clearly addresses only the combination of 21 22 Okada, Zakel, and the Lee Book. The parties’ discussion in the Intel Opp. at 23 and VLSI Reply 23 at 9 about whether Intel’s assertion of the combination of AAPA and the Lee Book is barred under 24 IPR estoppel is not properly before the Court and will not be considered. VLSI’s Motion for 25 Summary Judgment that IPR estoppel precludes Intel from relying on (4) Okada, Zakel, and the 26 Lee Book is granted; but the motion is denied with respect to a combination of AAPA and the Lee 27 Book (Fay Report ¶¶ 139–88). 28 \\ 10 1 2 Third, VLSI seeks summary judgment that IPR Estoppel bars Intel from using two 3 obviousness combinations for its purportedly improper reliance on physical products – (1) 4 Nehalem, Gunther, and Willingham (relied on by Dr. Apsel); and (5) Okada, the Lee Book, and 5 the Intel P1264 Package Process (relied on by Dr. Fay). 6 United States District Court Northern District of California c. The Nehalem Processor And P1264 Process While physical products cannot be raised during IPR proceedings, IPR estoppel can apply 7 to patents and printed publications, including those “that relate to and describe a physical 8 product.” Wasica Fin. GMbH v. Schrader Int’l, Inc., 432 F. Supp. 3d 448, 453 (D. Del. 2020). 9 That said, several courts have found that “reliance on some printed publications in an overall 10 collection of documents being used to describe a system invalidity theory should not lead to 11 estoppel of the overall system invalidity theory itself, nor piecemeal exclusion of the printed 12 publications underlying that system invalidity theory[.]” SPEX Techs. Inc. v. Kingston Tech. 13 Corp., 2020 WL 4342254, at *15 (C.D. Cal. June 16, 2020); CliniComp Int’l, Inc. v. 14 Athenahealth, Inc., 2020 WL 7011768, at *2 (W.D. Tex. Oct. 28, 2020) (finding no IPR estoppel 15 when the expert “does not rely solely on publicly available documents” but “opinions [we]re [also] 16 supported by non-public documents and other information that are not ‘printed publications’” that 17 could have been raised in IPR proceeding). 18 Several district courts have addressed whether printed materials that describe physical 19 products can be allowed. For example, one court found that a physical device cannot be used to 20 argue invalidity if the “material limitations” are disclosed in patents and printed publications; 21 another held the same if the physical device is “adequately described in” the printed publications. 22 Bos. Sci. Corp. v. Cook Grp. Inc., 2023 WL 1452172, at *34 (S.D. Ind. Jan. 31, 2023) (a defendant 23 cannot “us[e] a physical device to argue invalidity if all of the material limitations of that device 24 were disclosed in a patent or printed publication that the patent challenger either knew about or 25 reasonably could have discovered.”); Avanos Med. Sales, LLC v. Medtronic Sofamor Danek USA, 26 Inc., 2021 WL 8693677, at *2 (W.D. Tenn. Oct. 8, 2021) (where a defendant claims to rely on 27 “product” or “system” prior art, estoppel still applies when “the relevant claim limitations . . . [are] 28 adequately described in [] publicly available documents.”). 11 United States District Court Northern District of California 1 Furthermore, several courts have held that physical inspection is not always necessary, 2 particularly when a plaintiff “does not contend that the documentation fails to describe the product 3 accurately.” SiOnyx, LLC v. Hamamatsu Photonics K.K., 330 F. Supp. 3d 574, 604 (D. Mass. 4 2018); see also IOENGINE, LLC v. PayPal Holdings, Inc., 607 F. Supp. 3d 464, 512 (D. Del. 5 2022) (holding that the “expert need not have inspected or tested the devices in order to rely upon 6 them for purposes of invalidity” because “[c]ourts . . . have allowed the functions of prior art 7 devices to be established through the use of documents and testimony” (citing SiOnyx, 330 F. 8 Supp. 3d at 604). However, one court cautioned, “[i]f a defendant ‘purport[s] to rely on a device 9 without actually relying on the device itself’ . . . , the policy behind IPR estoppel may best be 10 served by excluding that reference.” In re Koninklijke Philips Pat. Litig., 2020 WL 7392868, at 11 *27 n.25 (N.D. Cal. Apr. 13, 2020). 12 13 i. Nehalem Processor VLSI seeks to bar Intel from using combination (1) Nehalem, Gunther, and Willingham. 14 VLSI argues that Dr. Apsel facially relies on the Nehalem Processor, but did not actually examine 15 a physical Nehalem product for her analysis and instead relied on Intel documents describing the 16 product. ECF No. 588-16 (Apsel Report Ex. B) at 1–26 (not listing any physical products as 17 “Materials Considered”). VLSI also argues that Dr. Apsel relies on the “Nehalem HC” and 18 “Nehalem IDF” slide decks for every element she opines that the Nehalem processor discloses in 19 her obviousness analysis. VLSI Mot. at 22; see, e.g., Apsel Report ¶ 777 (“Nehalem is a system- 20 on chip . . . as shown below [in Nehalem IDF].”), ¶ 793 (“As shown below [in Nehalem HC], each 21 Core, including Core 1 . . . is supplied by a voltage . . . through a power gating transistor[.]”). 22 VLSI further argues that the Nehalem HC and Nehalem IDF slide decks are publicly available 23 prior art publications that Intel disclosed in its March 19, 2018 Invalidity Contentions. VLSI Mot. 24 at 22 (citing Invalidity Contentions at 38–39). VLSI does acknowledge that Dr. Apsel’s Nehalem 25 obviousness analysis also includes citations to an “Intel Tech Journal” document dated in 2010, 26 after the undisputed 2009 priority date for the ’922 Patent, but argues that “The ‘Intel Tech 27 Journal’ document is not prior art, and Dr. Apsel relies on it exclusively to bolster her discussion 28 of Nehalem HC and Nehalem IDF.” Id. at 23 (citing Apsel Report ¶ 780). 12 United States District Court Northern District of California 1 In response, Intel argues that Dr. Apsel does not rely entirely on published materials, but 2 rather the Nehalem Processor as described in the Intel Tech Journal. Intel identifies vast citations 3 by Dr. Apsel to the Intel Tech Journal and argues that it discloses details regarding how the prior- 4 art Nehalem product worked before the ’922 Patent was filed. Intel Opp. at 18 (citing Apsel 5 Report at ¶¶ 780–83, 804, 807, 820–21, 827, 833, 836, 839–40, 844, 847, 851–52, 854–55, 860, 6 862, 870, 872, 890, 894, 902, 915, 921, 923, 930, 935–37, 940, 943, 946, 949, 953, 956–57, 959– 7 60). Intel then shows Dr. Apsel’s specific reliance “on infrared emission physical device images 8 of Nehalem from the Intel Tech Journal [and not found anywhere in the Nehalem HC or Nehalem 9 IDF presentations] as evidence that the Nehalem cores ‘[we]re controlled separately from the rest 10 of the SoC (the ‘uncore’) by powering [on or] off while the uncore remains powered.” Id. 11 (quoting Apsel Report ¶¶ 782–83, ECF No. 672-7 (“Intel Tech Journal”) at 56, 58–59). Intel 12 argues that Dr. Apsel also relies on an internal Intel Nehalem Microarchitectural Specification 13 (“MAS”) document that could not be used in an IPR proceeding because it is not a “printed 14 publication.” Id. The document purportedly “ 15 ” Id. at 19–20 (citing Apsel Report ¶ 824). 16 In reply, VLSI argues that none of the additional evidence describing the Nehalem 17 Processor is necessary for Dr. Apsel’s obviousness opinion. VLSI Reply at 12–13. VLSI attacks 18 paragraphs 780–83 of the Apsel Report for echoing the Nehalem HC and IDF presentations. As 19 for the MAS document, VLSI argues that Dr. Apsel uses the MAS solely to demonstrate the 20 background knowledge of a person of ordinary skill, and not as prior art. VLSI also argues that 21 “the fact that Dr. Apsel did not actually examine the Nehalem processor itself is strong evidence 22 that Intel and Dr. Apsel are using the Nehalem processor solely to circumvent IPR estoppel.” 23 VLSI Reply at 12; see Philips, 2020 WL 7392868, at *27 n.25, Medline Indus., Inc. v. C.R. Bard, 24 Inc., 2020 WL 5512132, at *5 (N.D. Ill. Sept. 14, 2020) (“[T]he petitioner cannot put forth 25 invalidity arguments in litigation that rely solely upon patents or printed publications that could 26 have been raised in the IPR, and then claim that IPR estoppel does not apply because these printed 27 materials reflect or represent a prior art product.”). 28 The Court agrees with Intel regarding Dr. Apsel’s reliance on the Intel Tech Journal. 13 United States District Court Northern District of California 1 Although VLSI lays out an argument for why four paragraphs (¶¶ 780–83) are duplicative of 2 Nehalem HC and Nehalem IDF, VLSI does not sufficiently address the remainder of Intel’s 3 citation to the Apsel Report. Apsel Report at ¶¶ 804, 807, 820–21, 827, 833, 836, 839–40, 844, 4 847, 851–52, 854–55, 860, 862, 870, 872, 890, 894, 902, 915, 921, 923, 930, 935–37, 940, 943, 5 946, 949, 953, 956–57, 959–60 (describing the product). The Court cannot parse and compare 6 each of these citations to Nehalem HC and Nehalem IDF without more from VLSI that shows that 7 the “material limitations of that device were disclosed” (Bos. Sci. Corp., 2023 WL 1452172, at 8 *34 or that the “relevant claim limitations . . . [are] adequately described” (Avanos, 2021 WL 9 8693677, at *2 ) in the two presentations. Furthermore, the Intel Tech Journal is not prior art 10 because it is dated in 2010, after the’922 Patent was filed on June 5, 2009. Intel Opp. at 18; ’922 11 Patent. Since the Intel Tech Journal is clearly not prior art and Intel could not have relied on it at 12 IPR, the motion is denied on this basis. SPEX, 2020 WL 4342254, at *15; CliniComp, 2020 WL 13 7011768 at *2. Furthermore, since the Intel Tech Journal could not be used in IPR, VLSI’s 14 argument that Dr. Apsel’s failure to inspect the Nehalem Processor suggests an attempt to 15 circumvent IPR estoppel is also not persuasive. Philips, 2020 WL 7392868, at *27 n.25; Medline, 16 2020 WL 5512132, at *5. 17 Thus, the Court concludes that a genuine dispute of material fact remains with respect to 18 whether combination (1) relies entirely on published prior art or also the Nehalem Processor as 19 described in the Intel Tech Journal. VLSI’s Motion for Summary Judgment that IPR estoppel 20 precludes Intel from relying on (1) Nehalem, Gunther, and Willingham is denied. 21 ii. P1264 Process 22 VLSI seeks to bar Intel from using combination (5) Okada, Lee Book, and Intel P1264 23 Package Process. VLSI similarly argues that Dr. Fay did not examine anything relating to the 24 P1264 Process for his analysis. ECF No. 588-17 (Fay Report App’x B) at 1–5 (not listing any 25 physical products as “Materials Considered”). VLSI also argues that Dr. Fay does not rely on the 26 P1264 Process to disclose any claim element that is not also disclosed by the Lee Book or Okada, 27 making the P1264 Process cumulative. Alternatively, VLSI argues that even if Dr. Fay’s use of 28 the P1264 Process was not duplicative of Okada and the Lee Book, the elements Dr. Fay draws on 14 1 the P1264 Process for were disclosed in prior art printed publications written by Intel engineers 2 (“Yeoh”), meaning Intel reasonably could have raised these same arguments during IPR. United States District Court Northern District of California 3 Intel responds that inspection is not a predicate to use and that “it would be particularly 4 unfair to do so in circumstances like here where Dr. Fay is relying on a prior art process used two 5 decades ago and no longer in use today.” Intel Opp. at 22. Intel further argues that it “can assert 6 invalidity based on grounds that might be ‘cumulative or redundant’ of grounds raised during IPR 7 as long as it does so by relying on references or combinations of references that were unavailable.” 8 Id. (quoting Contour IP Holding, LLC v. GoPro, Inc., 2020 WL 109063, at *6 (N.D. Cal. Jan. 9, 9 2020)); see also Pact XPP Schweiz AG v. Intel Corp., 2023 WL 2631503, at *6 (D. Del. Mar. 24, 10 2023) (“PACT tries to string together printed references that it claims are ‘cumulative’ of the 11 physical products. But PACT hasn’t pointed me to any legal basis to parse Intel’s legal 12 contentions to decide whether the physical device portion is ‘cumulative.’”). Intel also disputes 13 that the P1264 Process is cumulative because “Okada did not teach 14 P1264 Package Process.” Id. at 23 (quoting ECF No. 671-5 (“Fay Reply”) ¶ 38). Intel also argues 15 that “Yeoh was published in 2006—i.e., after VLSI’s claimed priority date of May 6, 2004 and the 16 April 28, 2005 U.S. filing date of the ’672 Patent” and therefore “Yeoh is not prior art, and thus 17 could not have been asserted as a prior art reference in the IPR.” Id. 18 used in the In reply, VLSI distinguishes Contour IP, arguing that “it was decided before the Federal 19 Circuit’s decision in Broadcom, and thus relied on now-outdated reasoning in determining that 20 estoppel did not prevent the defendant from raising prior art references cumulative of grounds 21 raised in the IPR.” VLSI Reply at 15. VLSI adds that “Dr. Fay never relies on 22 allegedly used in the P1264 Process for his invalidity arguments.” Id. (emphasis in original). 23 The Court agrees with Intel. Intel has shown that there are genuine factual disputes as to 24 whether Yeoh was available during IPR and whether Dr. Fay relied on the copper pillar in his 25 obviousness analysis. The Court need not settle the parties’ dispute over Contour IP because there 26 is a factual dispute over whether the physical prior art is cumulative. See Pact XPP, 2023 WL 27 2631503 at *6 (“Intel disputes whether the documents PACT cites were either available to it or 28 include all the relevant features of the physical product, and its expert will testify that the 15 1 combination of the physical and printed prior art is significant. I have no basis to disregard such 2 testimony and those references.”). On this basis, VLSI’s Motion for Summary Judgment that IPR 3 estoppel precludes Intel from relying on (5) Okada, the Lee Book, and the Intel P1264 Package 4 Process is denied. 5 6 Intel’s Motion Intel separately moves for summary judgment on the following grounds: (1) no 7 infringement of the ’836 Patent, (2) no infringement of the ’922 Patent, (3) invalidity of the 8 asserted claims for the ’922 Patent, (4) no infringement of the ’806 Patent, (5) no infringement of 9 the ’672 Patent, (6) that it is licensed to use the Asserted Patents, and (7) no willful infringement, 10 11 United States District Court Northern District of California B. 12 no indirect infringement, and no enhanced damages for any patent. 1. Infringement of the ’836 Patent VLSI accuses Intel’s Turbo Boost Max Technology 3.0 (“TBMT”) and “Thread Director” 13 of infringing claims 1, 9–11, 13, 17, 20, and 21 of the ’836 Patent. Intel Mot. at 1–2. Each of 14 Intel’s Accused Products includes multiple cores and a storage device that stores a processing 15 speed parameter (e.g., maximum measured frequency) for each core. ECF No. 579-4 (“Conte 16 Report”) ¶¶ 307–407. Each Accused Product also includes a power control unit (“PCU”) 17 functioning as the brains of the power management architecture, and includes hardware circuitry 18 and a microcontroller that runs special firmware code called Pcode (or p-code). Id. ¶ 278. 19 20 21 22 23 24 25 26 27 28 Claim 1 reads in relevant part: A method for operating a multi-core processing device, comprising: ... upon identifying a processing task that can not be run across the plurality of cores, selecting a core from the plurality of cores having a fastest measured processing speed parameter at a given voltage to run the processing task. ’836 Patent at 10:44–54 (emphasis added). Claim 20 reads in relevant part: In a multi-core processor comprising multiple cores . . . a method for executing single core applications and multi-core applications comprising: . . . running a single core application on a single core which is identified from the stored maximum processing speed values for the multiple cores as being the fastest core upon identifying a processing task that 16 1 2 Id. at 12:17–30 (emphasis added). Claim 10 contains similar language: 3 A multi-core system on chip (SOC), comprising: . . . 4 6 at least a first storage device for storing the performance parameter values for the plurality of cores for use in selecting a core having maximized or minimized performance parameter value at a specified voltage to run a processing task that can not be run across the plurality of cores. 7 Id. at 11:19–29 (emphasis added). In its Markman Order, the Court construed claim 10 to include 8 the same “upon identifying” limitation as claims 1 and 20. Markman Order at 22–25. Claim 9 9 depends on claim 1; claims 11, 13, and 17 depend on claim 10; and claim 21 depends on claim 20. 5 10 United States District Court Northern District of California cannot be run across the plurality of the multiple cores. Intel makes three arguments that TBMT and Thread Director do not infringe the ’836 11 Patent: (1) there is no literal infringement (id. at 3–4); (2) there is no infringement under the 12 doctrine of equivalents (“DOE”) (id. at 4–6); and (3) there is no infringement because testing 13 occurs outside the United States (id. at 6–8). The Court addresses the three arguments in turn. 14 15 a. Literal Infringement Intel first argues that the plain language of the “upon identifying” limitation (claims 1, 9– 16 11, 13, 17) and “identifying” limitation (claims 20, 21) specify that selecting the core to run a 17 single-core task occurs only after identification of the task as a single-core task. Intel Mot. at 3–4. 18 Intel cites evidence that VLSI argued that the claims contain a temporal requirement that the task 19 is identified as single-core before a core is selected. ECF No. 143 (VLSI Markman Brief) at 20 20 (agreeing “upon identifying” is “a temporal term that describes when something happens”) 21 (emphasis added); ECF No. 145 (Conte Markman Decl.) ¶ 181 (same); ECF No. 158-13 (“’836 22 File History”) at 1934 (Examiner requiring applicants “to amend independent claims 1, 10, and 20 23 to clarify that a core is selected from the plurality of cores when it is identified that a task cannot 24 be run across the plurality of cores” as a condition for allowing the patent to issue) (emphasis 25 added). Intel also cites to depositions of several fact witnesses as evidence that “the accused 26 products never identify whether a task is a single-core task—let alone before selecting a core for 27 the task.” Intel Mot. at 3 (citing ECF No. 580-5 (Ramani Dep.), ECF No. 579-6 (McGavock 28 Dep.), ECF No. 580-8 (Therien 1/27/23 Dep.), ECF No. 580-9 (Chen Dep.), ECF No. 579-7 (L. 17 1 Brown Dep.), ECF No. 579-8 (Fenger Dep.), ECF No. 579-9 (T. Brown Dep.)). Intel then attacks 2 VLSI expert Dr. Thomas M. Conte’s opinion, writing that Dr. Conte points only to an 3 identification process that “occurs after a core has already been selected or identified.” Intel Mot. 4 at 4 (citing Conte Report ¶¶ 416–17, 427, 433, 439, 448, 454, 460, 466), ECF No. 579-5 (Conte 5 Dep.) 136:23–139:23, 138:2–15), United States District Court Northern District of California 6 VLSI responds that Intel mischaracterizes Dr. Conte’s infringement opinion. VLSI Opp. at 7 3. VLSI argues that “Dr. Conte does not contend that the OS-based scheduler software alone 8 performs the ‘selecting’ step” but instead “the step is performed by the combination of the OS 9 software working together with the PCU’s Pcode.” Id. (citing Conte Report ¶ 417). VLSI also 10 points to Dr. Conte’s deposition, where he “repeatedly refuted the central premise of Intel’s 11 motion, that ‘what Dr. Conte points to in the accused products as identifying a single-core task 12 (i.e., the code determining how many cores are active) occurs after a core has already been 13 selected or identified.’” Id. (citing ECF No. 579-5 (Conte Dep.) 135:12–136:2, 134:17–135:11, 14 136:12–140:6). VLSI also dismisses the fact witness testimony, stating that it “only focused on 15 the OS scheduler in isolation and not the operation of the system as a whole, including the 16 involvement of the Pcode in the ‘selecting’ step” and that “many of these witnesses testified that 17 they were not familiar with or had not seen the Accused Products’ Pcode.” VLSI Opp. at 4. 18 Intel replies that it’s not about “which components are involved in the accused 19 identifying/selecting steps, including the role of p-code” but rather, “the order that the accused 20 identifying/selecting steps occur, not which components or p-code are involved in those steps.” 21 Reply at 1. To that, Intel argues, “the undisputed evidence shows that Intel’s accused products do 22 not select a core after identifying a single-core task as required by the ‘upon identifying’ 23 limitation.” Id. 24 25 26 27 28 The Court agrees with VLSI. Dr. Conte’s report opines that the p-code works in conjunction with the OS to pick a single favored core to run a single active thread: In . . . TBMT and Thread Director, Pcode working in conjunction with Intel-authored software (for OS versions 7, 8, and 10 TH1), and/or the OS, performs the step of “selecting a core . . . to run the processing task.” Pcode in an accused processor provides core diversity information (e.g., measured max frequency of each core) to the Intel18 authored software and/or OS, which in turn causes a single-active thread to be scheduled on a “favored” core (e.g., a core having a fastest frequency) based on the core diversity information received from the Pcode. 1 2 3 Conte Report at ¶ 417 (emphasis added). Dr. Conte’s report then states that the selecting step is 4 performed “upon identifying the single core task.” Id. He continues: Further, the “selecting” claim step is performed “upon identifying a single core task.” Pcode working in conjunction with Intel-authored software and/or the OS identifies a single-core task. In particular, the Intel-authored software and/or OS schedules a thread on the favored core (e.g., as explained herein), and the remaining cores enter sleep states. The Pcode detects that the favored core is the only active core (e.g., the only core in C0 state), and causes the favored core to run the scheduled single-core task at the fastest measured operating frequency at a given voltage. 5 6 7 8 United States District Court Northern District of California 9 10 Id. (emphasis added). Contrary to Intel’s argument (Mot. at 4), the Court finds that Dr. Conte’s 11 report is evidence that the accused technology identifies a task, then selects a core to run that task. 12 Dr. Conte’s deposition testimony does not fatally undermine the conclusion in his report. 13 For example, when Dr. Conte is asked about core selection for a single-core task, Dr. Conte states 14 that “the p-code presents diversity information to the operating system which allows that operating 15 system to select the favored core.” ECF No. 579-5 (Conte Dep.) 139:12–15. The Court finds that 16 Dr. Conte’s report and deposition testimony create a genuine dispute of material fact as to whether 17 TBMT and Thread Director meet the “upon identifying” claim limitation. Thus, Intel’s Motion 18 for Summary Judgment of no literal infringement of the ’836 Patent for failure to meet the 19 temporal limitation is denied. 20 21 b. Doctrine of Equivalents VLSI presents a theory under the doctrine of equivalents (DOE) where the “selecting” step 22 can occur “upon or substantially simultaneously with identifying a single core task” (instead of 23 upon identifying a single core task). VLSI Opp. at 7 (quoting Conte Report ¶¶ 471–72). Intel 24 makes three arguments that VLSI’s DOE theory fails as a matter of law: amendment-based 25 estoppel, argument-based estoppel, and claim vitiation. Intel Mot. at 4–6. The Court addresses 26 each in turn. 27 28 i. Amendment-Based Estoppel First, Intel argues that “amendment-based prosecution history estoppel forecloses VLSI 19 United States District Court Northern District of California 1 from alleging any broader scope for this claim limitation under the DOE.” Id. at 4–5. Intel 2 explains that “[d]uring prosecution, claim 20 was narrowed by amendment to add the limitation 3 ‘upon identifying a processing task that cannot be run across the plurality of the multiple cores.’” 4 Id. at 4 (quoting ’836 File History at 1941). Intel continues that “[t]he applicants relied on [the 5 multiple cores] claim language during prosecution to distinguish the prior art that disclosed 6 selecting cores for other reasons.” Id. at 4–5 (citing ’836 File History). 7 VLSI argues that the Applicant’s agreement to amend claim 20 does not trigger 8 prosecution history estoppel because the clarifying amendment was not made to overcome the 9 prior art. VLSI Opp. at 5. VLSI continues that “the addition of ‘upon identifying’ to claim 20 10 ‘did nothing more than make express what had been implicit in the claim as originally worded,’ as 11 this language had been present in claims 1 and 10 from the beginning.” Id. (quoting Interactive 12 Pictures Corp. v. Infinite Pictures, Inc., 274 F.3d 1371, 1377 (Fed. Cir. 2001)). 13 VLSI argues alternatively that “amendment to claim 20 does not trigger prosecution 14 history estoppel because the order or timing of events (upon identifying before selecting) had 15 nothing to do with the Examiner’s initial rejection of the claims.” VLSI Opp. at 6. Rather, “[t]he 16 issue was whether the prior art disclosed the ‘identifying’ limitation at all.” Id. (citing ’836 File 17 History at 1877–79, 1904–06, 1913–1916). 18 Intel replies that the “amendment (1) added an entirely new temporal limitation to claim 19 20, and (2) arose from an Examiner interview discussing the obviousness of the claim (over the 20 prior art Bernstein reference), after which the Examiner expressly conditioned allowance of the 21 claim on making the amendment.” Intel Reply at 2. 22 The Court agrees with VLSI. As VLSI notes, claims 1 and 10 were not narrowed during 23 prosecution. VLSI Opp. at 5 (citing ’836 File History at 1824–25). The only independent claim 24 where this language was added is claim 20. Furthermore, VLSI presents evidence that the 25 examiner withdrew the rejection of all claims and suggested that “upon identifying” is clarifying 26 language. Id. (citing ’836 File History at 1928, 1934, 1936, 1938–41). Thus, the Court finds that 27 this evidence creates a genuine issue of material fact that forecloses a finding of amendment-based 28 estoppel at summary judgment. 20 ii. United States District Court Northern District of California 1 Argument-Based Estoppel 2 Second, Intel argues that “argument-based prosecution history estoppel also bars VLSI’s 3 equivalents theory” because of VLSI’s “repeated reliance on the ‘upon identifying’ limitation to 4 distinguish every asserted claim from the prior art during prosecution.” Intel Mot. at 5 (citing 5 ’836 File History). Intel’s motion points to several parts of the ’836 File History where the 6 applicant claimed a temporal aspect. Intel Mot. at 5; see, e.g., ’836 File History at 1877 (applicant 7 stating “claims 1, 10, and 20” all require “upon identifying a single-core processing task that 8 cannot be run by the plurality of cores, the core having the fastest measured processing speed 9 parameter is selected to run the identified single-core processing task”); id. at 1913–14 (same); id. 10 at 1934 (“It was agreed to amend independent claims 1, 10, and 20 to clarify that a core is selected 11 from the plurality of cores when it is identified that a task cannot be run across the plurality of 12 cores.”). 13 VLSI responds that its “DOE theory does not eliminate the identification of a single core 14 task, but rather concerns its timing with respect to the ‘selecting’ step” and specifically, “that 15 ‘selecting’ can occur ‘upon or substantially simultaneously with identifying a single core task.’” 16 VLSI Opp. at 7 (quoting Conte Report ¶¶ 471–72). VLSI specifically refutes the citation to page 17 1934 of the prosecution history, stating that it is not enough that “the Examiner used the term 18 ‘when’ in interview summary” because “the interview focused on changing the word ‘by’ to 19 ‘across,’ and the word ‘when’ was not added to the claims.” VLSI Opp. at 7; ’836 File History at 20 1934, 1936, 1938–41. 21 In its reply, Intel adds a fourth citation to the file history. Intel Reply at 3 (quoting ’836 22 File History at 1876) (“[A] ‘single core’ processing task is identified. Once a ‘single core’ task is 23 identified (a.k.a., a processing task that cannot be run by the plurality of cores), the claimed 24 methodology selects the fastest core to run the ‘single core’ task.”). 25 The Court agrees with VLSI. “To invoke argument-based estoppel, ‘the prosecution 26 history must evince a clear and unmistakable surrender of subject matter.” Amgen, Inc. v. Coherus 27 BioSciences, Inc., 931 F.3d 1154, 1159 (Fed. Cir. 2019) (quoting Conoco, Inc. v. Energy & Envtl. 28 Int'l, L.C., 460 F.3d 1349, 1364 (Fed. Cir. 2006)). “Clear assertions made during prosecution in 21 1 support of patentability, whether or not actually required to secure allowance of the claim, may 2 also create an estoppel . . . the relevant inquiry is whether a competitor would reasonably believe 3 that the applicant had surrendered the relevant subject matter.” Id. at 1159–60 (quoting PODS, 4 Inc. v. Porta Stor, Inc., 484 F.3d 1359, 1368 (Fed. Cir. 2007)) (cleaned up). United States District Court Northern District of California 5 The four statements put forth by Intel are not enough to prevail at summary judgment. The 6 first two merely recite claim language. ’836 File History at 1877 (applicant stating “claims 1, 10, 7 and 20” all require “upon identifying a single-core processing task . . .”); id. at 1913–14 (same). A 8 finding that a recitation of claim language alone would estop an equivalent theory of infringement 9 would undo the doctrine of equivalents. The third citation, that “a core is selected from the 10 plurality of cores when it is identified that a task cannot be run across the plurality of cores” is also 11 not enough. As VLSI argues, the word “when” was provided by the examiner, not the applicant. 12 Finally, the Court does not consider the fourth citation (’836 File History at 1876) because Intel 13 did not raise it until its reply brief, and has therefore waived the argument. Thus, the Court finds 14 that this evidence creates a genuine issue of material fact that forecloses a finding of argument- 15 based estoppel at summary judgment. 16 iii. 17 Claim Vitiation Intel’s final argument is that VLSI’s DOE theory would vitiate the Asserted Claims of the 18 ’836 Patent. The doctrine of claim vitiation “ensures that ‘the application of the doctrine of 19 equivalents is not allowed such broad play as to effectively eliminate a claim element in its 20 entirety.’” Bio-Rad Lab'ys, Inc. v. 10X Genomics Inc., 967 F.3d 1353, 1366 (Fed. Cir. 2020) 21 (quoting Warner-Jenkinson Co. v. Hilton Davis Chem. Co., 520 U.S. 17, 29 (1997)) (cleaned up). 22 Vitiation “is not an exception or threshold determination that forecloses resort to the doctrine of 23 equivalents, but is instead a legal conclusion of a lack of equivalence based on the evidence 24 presented and the theory of equivalence asserted.” Id. at 1366–67 (quoting UCB, Inc. v. Watson 25 Labs., Inc., 927 F.3d 1272, 1283 (Fed. Cir. 2019)). “[S]aying that a claim element would be 26 vitiated is akin to saying that there is no equivalent to the claim element in the accused device 27 based on the well-established ‘function-way-result’ or ‘insubstantial differences’ tests.” Id. at 28 1366–67 (quoting Brilliant Instruments, Inc. v. GuideTech, LLC, 707 F.3d 1342, 1347 (Fed. Cir. 22 1 United States District Court Northern District of California 2 2013)). “The vitiation test cannot be satisfied merely by noting that the equivalent substitute is 3 outside the claimed limitation's literal scope.” Brilliant, 707 F.3d at 1347. Rather, “vitiation 4 comes into play when the alleged equivalent is 'diametrically opposed to the missing claim 5 element.” Bio-Rad, 967 F.3d at 1367 (internal quotations omitted). One way to show a claim is 6 vitiated is “if the theory or evidence of equivalence is legally incapable of establishing that the 7 differences between the limitation in the claim and the accused device are insubstantial; i.e., if the 8 theory or evidence is so legally insufficient as to warrant a holding of non-infringement as a matter 9 of law.” Id. (quoting DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1017 10 (Fed. Cir. 2006)). “If the claimed and accused elements are recognized by those of skill in the art 11 to be opposing ways of doing something, they are likely not insubstantially different.” Id. 12 (quoting Brilliant, 707 F.3d at 1347–48). 13 Intel argues that VLSI’s DOE theory “would vitiate the ‘upon identifying’ limitation by 14 allowing the claims to be met if a single-core task is sent to the fastest core for any reason, 15 including those having nothing to do with whether the task is a single-core task.” Intel Mot. at 6. 16 VLSI responds that under its DOE theory, “the claims are met if a single-core task is 17 identified substantially simultaneously with selecting the fastest core to run the single-core task” 18 because “when a single-core task is identified and placed on the fastest (favored) core, the core’s 19 clock frequency is boosted to its maximum measured frequency, which is higher than the 20 maximum measured frequency of the non-favored cores.” VLSI Opp. at 7 (citing Conte Report ¶¶ 21 417, 471–472). 22 The Court agrees with Intel that VLSI’s DOE theory where a single-core task can be 23 identified “substantially simultaneously” would vitiate the claims. The literal meaning of the 24 claim limitations requires the two-step process of first identifying the task and then selecting the 25 core. VLSI’s “substantially simultaneously” theory allows for any “ordering of the identification 26 and selection steps—such that the identification step could occur before, after, or simultaneously 27 with the selection step.” See Intel Reply at 3. That is not merely interchangeable or outside the 28 claimed limitation's literal scope, but would “effectively eliminate” the upon identifying “claim 23 1 element in its entirety.” Bio-Rad, 967 F.3d at 1366. VLSI’s explanation that a core’s frequency 2 can be boosted does not save its theory. That a core can be sped up has nothing to do with the 3 order in which the steps in a process are accomplished, and thus says nothing about whether the 4 equivalent process is “substantially similar” to the literal process. 5 6 Patent, the Court finds that VLSI’s DOE theory fails as a matter of law. Intel’s Motion for 7 Summary Judgment of no infringement of the ’836 Patent under the doctrine of equivalents is 8 granted. 9 10 United States District Court Northern District of California Having found as a matter of law that it would vitiate the Asserted Claims of the ’836 c. Testing Outside the Country Intel argues that the Court should find no infringement of the ’836 Patent because certain 11 limitations were infringed only outside the United States. Among the Asserted Claims are four 12 method claims (claims 1, 9, 20, and 21) and four apparatus claims (claims 10–11, 13, and 17). 13 The Court addresses the method claims, then the apparatus claims. 14 i. Method Claims 15 “A defendant can only directly infringe a method claim . . . by ‘using’ the method within 16 the United States, which requires that the defendant practice every step of the method within the 17 United States.” France Telecom S.A. v. Marvell Semiconductor Inc., 82 F. Supp. 3d 987, 993 18 (N.D. Cal. 2015) (citing Meyer Intellectual Properties Ltd. v. Bodum, Inc., 690 F.3d 1354, 1366 19 (Fed. Cir. 2012)); NTP, Inc. v. Research In Motion, Ltd., 418 F.3d 1282, 1318 (Fed. Cir. 2005) 20 (“[A] process cannot be used ‘within’ the United States as required by section 271(a) unless each 21 of the steps is performed within this country.”), abrogated on other grounds, see IRIS Corp. v. 22 Japan Airlines Corp., 769 F.3d 1359, 1361 n.1 (Fed. Cir. 2014). 23 Claims 1, 9, 20, and 21 recite methods that, among other things, require “measuring” the 24 processing speed of each core in a multicore processor. According to Intel, “VLSI alleges that 25 Intel performs the claimed ‘measuring’ step only when Intel tests its products during 26 manufacturing.” Intel Mot. at 6 (citing Conte Report ¶¶ 307–63, 541–45, ECF No. 579-5 (Conte 27 Dep.) 84:8–85:23). Intel, however, argues that “it is undisputed that Intel performs this testing 28 exclusively in Costa Rica and Malaysia. Id. (citing ECF No. 580-7 (Therien 1/26/23 Dep.) 24 1 181:17–25, ECF No. 580-8 (Therien 1/27/23 Dep.) 399:20–400:9, ECF No. 580-13 (“Cavagnaro 2 Dep.”) 158:16–159:19, 160:19–161:6, Johnson Dep. 41:23–25). 3 4 as evidence that “Intel meets the technical requirements of the ‘measuring’ limitation.” VLSI 5 Opp. at 8 (citing Conte Report ¶¶ 307–63). Second, VLSI argues that Intel stipulated that 70% of 6 the activities that meet the technical requirements are deemed to have a U.S. nexus under 35 7 U.S.C. 271(a). The stipulation states: 8 11 Of the total, global number of Intel products and associated activities determined (without regard to geographic considerations) to meet the technical requirements of any asserted VLSI patent claim not proven invalid by Intel[,] . . . seventy percent (70%) thereof will be deemed to have a United States nexus as required by each subsection of 35 U.S.C. § 271 and for determining any patent infringement damages in this case. . . . 12 ECF No. 581-2 (“U.S. Nexus Stip.”) at 2. VLSI argues that “[t]he stipulation forecloses Intel from 13 arguing that it does not infringe solely due to geographical considerations, which is what Intel is 14 arguing here.” VLSI Opp. at 8. 9 10 United States District Court Northern District of California VLSI responds in two parts. First, VLSI points to a 33-page excerpt of the Conte Report 15 The Court agrees with Intel. As an initial matter, VLSI has not pointed the Court to any 16 evidence from Dr. Conte’s Report that the testing occurs in the United States. In the only part of 17 the lengthy excerpt provided to the Court that addresses the location of testing, Dr. Conte does not 18 dispute that testing occurs outside the United States. Conte Report at ¶ 322 (“HVM testing is 19 developed in Oregon and sent out to the Intel manufacturing facilities across the world.”). Dr. 20 Conte’s report does not supply evidence of testing occurring inside the United States, and in fact is 21 an acknowledgement that testing occurs outside the United States. 22 Instead, VLSI relies entirely on the stipulation for its argument that the testing is deemed 23 to have occurred inside of the United States. But the stipulation expressly states that it is not an 24 admission of infringement. U.S. Nexus Stip. at 2 (“By entering into this agreement, neither party 25 makes any admission about patent infringement . . . .”); id. (“This agreement does not in any way 26 suggest or indicate that any of the Intel products at issue infringe . . . .”). Furthermore, the 27 stipulation states that the nexus only applies to products determined to meet the technical 28 requirements of any asserted claim, such as infringement. Id. ("Of the total, global number of 25 1 Intel products and associated activities determined (without regard to geographic considerations) 2 to meet the technical requirements of any asserted VLSI patent claim . . . will be deemed to have a 3 United States nexus.”). One of the technical requirements necessary for the nexus to apply is that 4 the claim limitations are met (in the United States). Since the testing limitation is a condition of 5 finding nexus under the stipulation, the stipulation cannot be used as evidence of meeting the 6 testing limitation. Thus, the Court concludes that the stipulation is not evidence that Intel meets 7 the testing limitation. United States District Court Northern District of California 8 Having found that VLSI’s evidence does not create a genuine dispute of material fact as to 9 whether the testing limitation occurs in the United States, the Court finds as a matter of law that 10 VLSI cannot prove that Intel infringes claims 1, 9, 20, and 21 of the ’836 Patent. Thus, Intel’s 11 Motion for Summary Judgment of no infringement of claims 1, 9, 20, and 21 of the ’836 Patent is 12 granted. 13 14 ii. Apparatus Claims “[W]here claim language recites ‘capability, as opposed to actual operation,’ an apparatus 15 that is ‘reasonably capable’ of performing the claimed functions ‘without significant alterations’ 16 can infringe those claims.” INVT SPE LLC v. Int'l Trade Comm'n, 46 F.4th 1361, 1375–76 (Fed. 17 Cir. 2022) (quoting ParkerVision, Inc. v. Qualcomm Inc., 903 F.3d 1354, 1362 (Fed. Cir. 2018)). 18 Claims 10, 11, 13, and 17 recite a “system on a chip” that, among other things, contains “a 19 performance measurement circuit for measuring a performance parameter value for said core.” 20 ’836 Patent at 11:20–23 (emphasis added). VLSI alleges that “the accused products contain 21 circuitry that satisfies this ‘measuring’ limitation.” See Intel Mot. at 7 (citing Conte Report ¶ 493). 22 However, Intel argues “it is undisputed that the accused circuitry is only used for measuring values 23 when connected to an external testing device called an ‘ATE tester’ that is part of Intel’s 24 manufacturing facilities in Costa Rica and Malaysia.” Id. (citing Cavagnaro Dep. 158:16–159:19, 25 160:19–161:6, 166:16–167:8, 170:2–171:18, ECF No. 579-5 (Conte Dep.) 109:21–110:6, Conte 26 Report ¶ 339). 27 28 VLSI responds that “[t]he ATE tester is not a required component of the claimed ‘performance measurement circuit.’” VLSI Opp. at 9. As evidence, VLSI cites to the Conte 26 United States District Court Northern District of California 1 Report, which states, “Each core includes performance measurement circuitry used for running 2 various tests to measure the operational frequencies and corresponding voltages of each core. The 3 performance measurement circuitry includes critical path monitoring circuitry for testing critical 4 paths used for measuring such frequencies and voltages.” Conte Report ¶ 339. VLSI also claims 5 that Dr. Conte explains in his deposition that Intel meets the technical requirements of the 6 “performance measurement circuit” limitation irrespective of any testing by Intel. VLSI Opp. at 9 7 (citing ECF No. 579-5 (Conte Dep.) 108:17–113:18). VLSI then claims that “Intel’s reliance on 8 [INVT], is misplaced because each Accused Product includes ‘a performance measurement circuit 9 for measuring a performance parameter value for said core.’” VLSI Opp. at 9 (citing Conte Report 10 at ¶ 339). As a fallback, VLSI relies on its global stipulation, (which the Court has rejected, see 11 supra). 12 The Court agrees with Intel. The claim limitation that the circuit is “for measuring” (’836 13 Patent at 11:20–23) points to “capability, as opposed to actual operation”, so “an apparatus that is 14 reasonably capable of performing the claimed functions without significant alterations can infringe 15 those claims.” INVT, 46 F.4th at 1375–76 (citations and quotations omitted). The question then is 16 whether the accused technology is “reasonably capable” of performing the claimed functions. 17 Ibid. VLSI has presented evidence that the accused technology contains a “performance 18 measuring circuit” but puts forth no evidence that the accused technology is capable of “measuring 19 a performance parameter” (’836 Patent at 11:20–23) except when used with ATE testers. See 20 Conte Report ¶ 339 (“Intel uses an ATE tester as part of the test apparatus”). And, as discussed 21 supra, VLSI has put forth no evidence that ATE testing is performed in the United States. When 22 asked if the “performance measurement circuits can be used for measuring a performance 23 parameter value when not connected to [an ATE] tester,” Dr. Conte replied that he had not 24 “opined one way or the other.” ECF No. 579-5 (Conte Dep.) 111:4–112:24. Dr. Conte further 25 admitted that he “had not sought any evidence” when asked whether “anyone actually has used the 26 performance measurement circuit for measuring a performance parameter value when not 27 connected to a tester.” Id. Thus, there is no evidence that the accused technology is reasonably 28 capable of meeting the testing claim limitation in the United States. Having found that VLSI’s 27 1 evidence does not create a genuine dispute of material fact as to whether the testing limitation 2 occurs in the United States, the Court finds as a matter of law that VLSI cannot prove that Intel 3 infringes claims 10, 11, 13, and 17 of the ’836 Patent. Thus, Intel’s Motion for Summary 4 Judgment of no infringement of claims 10, 11, 13, and 17 of the ’836 Patent is granted. 5 United States District Court Northern District of California 6 2. Infringement of the ’922 Patent VLSI accuses Intel of infringing claims 4, 5, and 18 of the ’922 Patent. Claim 1 (upon 7 which claims 4 and 5 depend) recites, “A power island for a system-on-a-chip (SoC), the power 8 island comprising: . . . a supply line to receive an external supply signal (VDD)[.]” ’922 Patent at 9 9:10–21 (emphasis added). Claim 4 further recites, “The power island of claim 1, further 10 comprising a reference line to receive a reference signal (VSS)[.]” Id. at 9:50–51 (emphasis 11 added). Claim 5 further recites: 12 The power island of claim 4, wherein: 13 the supply power converter comprises a VDD switch with a first added resistance to cause a first voltage drop and reduce the supply voltage of the external supply signal to the second voltage of the second power characteristics; and 14 15 16 17 18 19 20 21 22 23 the reference power converter comprises a VSS switch with a second added resistance to cause a second voltage drop and change the reference voltage consistent with the second power characteristics. Id. at 9:62–10:4 (emphasis added). Claim 17 (upon which claim 18 depends) recites: A method for making a power island for a system-on-a-chip (SoC), the method comprising: coupling a memory device to a supply line of the power island, wherein the supply line is configured to receive an external supply signal (VDD) from an external power control to operate the memory device according to first power characteristics; Id. at 11:41–12:5 (emphasis added). Claim 18 further recites: 24 The method of claim 17, further comprising: coupling the logic . . . . 25 coupling a reference power converter to the the reference power converter is configured power characteristic of a reference signal internal reference signal (VSSi) according characteristics; 26 27 28 Id. at 12:19–27 (emphasis added). 28 logic module, wherein to change at least one (VSS) to generate an to the second power United States District Court Northern District of California 1 Intel seeks summary judgment of no infringement because it argues that VLSI has failed 2 “to identify anything in Intel’s accused products that constitutes converting a ‘VSS’ reference 3 signal—a requirement of each asserted claim.” Intel Mot. at 8. Intel argues, and VLSI does not 4 dispute, that VLSI technical expert Dr. William Henry Mangione-Smith accuses a signal called 5 “VCCIN” (also called “Vcc” or “Vin”) of meeting both the “external supply signal (VDD)” and 6 “reference signal (VSS)” limitations. Intel Mot. at 8; ECF No. 579-10 (“Mangione-Smith Suppl. 7 Report”) ¶¶ 197–202, 207–16, 227–47; ECF No. 579-11 (“Mangione-Smith Dep.”) 73:4–77:19, 8 94:11–95:13, 127:12–134:12. Intel makes two arguments as to why this supports a finding of no 9 infringement. First, Intel makes a claim construction argument that the term “reference signal” is 10 limited by the parenthetical term “VSS.” Second, Intel argues that Dr. Mangione-Smith’s theory 11 is internally contradictory. The Court addresses the arguments in turn. 12 13 14 15 a. Whether “VSS” is an Express Claim Limitation Intel’s first argument is that “VSS” is an express claim term and therefore limits the type of “reference signal” to a particular type of signal, “VSS.” Intel Mot. at 10. “The mere fact that a limitation is placed within parentheses does not mean it is no longer a 16 part of the claim.” Janssen Pharmaceutica, N.V. v. Eon Labs Mfg., Inc., 134 F. App’x 425, 428 17 (Fed. Cir. 2005). In Janssen, the Federal Circuit considered whether the claim language 18 describing a sieve, “600 to about 700 μm (25–30 mesh),” was limited by the term “(25–30 mesh)” 19 even though it was in parentheses. Id. at 428. The first part, “600 to about 700 μm,” referred to 20 dimensions of a sieve, and the parenthetical, “(25–30 mesh),” referred to the size of the bead 21 cores, an additional characteristic of the sieve. Id. at 428–429. The court concluded that “one 22 having ordinary skill in this art would interpret ‘a diameter of from about 600 to 700 μm (25–30 23 mesh)’ to describe cores 1) labeled 25–30 mesh at the time of manufacture and classification, and 24 2) having a particular diameter, about 600–700 μm.” Id. The court further reasoned that if it were 25 to “conclude that claim 1 simply covers all cores having a diameter 600–700 μm across the center 26 [it] would be rendering the phrase ‘25–30 mesh’ superfluous.” Id. at 428. 27 28 Intel argues that “the stated purpose of the reference power converter is specifically to change ‘VSS’ by a certain amount purportedly to simplify communications within the power 29 1 island.” Intel Mot. at 10; ’922 Patent at 7:34–49; 7:57–8:7; Figure 4 (showing VSS being raised 2 from 0.0V to 0.2V). Intel adds that the specification consistently describes using “VSS” as the 3 reference signal—in every single embodiment. E.g., ’922 Patent at 5:10–17, 6:64–65, 7:50–54, 4 8:26–53 (“reference signal, VSS”); Figs. 1–7 (all describing the “reference signal” as “VSS”); 5 ECF No. 579-14 (“Apsel Rebuttal Report”) ¶¶ 55–60, 63–67, 144–167. Intel further notes that 6 claim 5, which depends on claim 4, “specifically recites a ‘VSS switch’ as part of the ‘reference 7 power converter.’” ’922 Patent at 10:1–4. Intel argues that claim 5’s “switch” is a “VSS switch” 8 because “it switches the ‘VSS’ signal recited in claim 4,” which “further confirm[s] that ‘VSS’ in 9 claim 4 is limiting.” Intel Mot. at 11. United States District Court Northern District of California 10 VLSI responds that “Intel does not offer any evidence that a limiting ‘VSS’ would exclude 11 the accused ‘reference signal’ or explain what it contends the term would mean.” VLSI Opp. at 12 11. Rather, VLSI argues, the parenthetical in “reference signal (VSS)” refers to examples of the 13 “reference signal” that are labeled “VSS” in the specification and figures, without incorporating 14 every feature of these examples into the claims. VLSI Opp. at 11–12 (citing Core Wireless 15 Licensing S.A.R.L. v. LG Elecs., Inc., 2015 WL 6956722, at *5, *7 (E.D. Tex. Nov. 9, 2015), 16 Hochstein v. Microsoft Corp., 2009 WL 1838975, at *12–16 (E.D. Mich. June 22, 2009)). VLSI 17 also puts forth a theory that “VSS” is a “reference character” and is thus “considered as having no 18 effect on the scope of the claims.” VLSI Opp. at 12 (quoting MPEP § 608.01(m)). As for the 19 later instances of a non-parenthesized “VSS,” VLSI argues that claim 5’s “VSS switch” refers to 20 one of two separately recited switches (the other a “VDD switch”), which VLSI argues its expert 21 identifies separately. See Mangione-Smith Suppl. Report ¶¶ 249–57; ECF No. 579-12 (Mangione- 22 Smith Reply Report) ¶¶ 160–62. 23 It is clear from the parties' discussion of this issue that infringement depends on further 24 claim construction and the parties have adequately set out their respective positions. General 25 Mills, Inc. v. Hunt-Wesson, Inc., 103 F.3d 978, 983 (Fed. Cir. 1997). Intel urges a construction 26 that “reference signal (VSS)” is limited to a particular type of signal, VSS. Intel Mot. at 10. VLSI 27 argues that (VSS) only refers to examples of the “reference signal” and is not limiting. VLSI Opp. 28 at 11–12. 30 United States District Court Northern District of California 1 Intel persuasively argues that the term “reference signal” is limited by the term “(VSS).” 2 The specification uses the term “reference signal” eight times, and seven of those times the term is 3 accompanied with the term VSS. ’922 Patent at 5:11 (“reference signal, VSS”), 5:13 (same), 4 5:16–17 (same), 6:64–65 (same), 7:52 (same), 8:45 (same), 8:52 (same), 6:59 (“reference voltage, 5 VSS, of the reference signal”). Furthermore, if the term “VSS” did not limit “reference signal,” 6 “VSS” would be given no effect. Janssen, 134 F. App’x at 428; Phillips v. AWH Corp., 415 F.3d 7 1303, 1312 (Fed. Cir. 2005) (“It is a ‘bedrock principle’ of patent law that ‘the claims of a patent 8 define the invention to which the patentee is entitled the right to exclude.’”); Intel Corp. v. 9 Qualcomm Inc., 21 F.4th 801, 810 (Fed. Cir. 2021) (“It is highly disfavored to construe terms in a 10 way that renders them void, meaningless, or superfluous.”); Bicon, Inc. v. Straumann Co., 441 11 F.3d 945, 950 (Fed. Cir. 2006) (“[C]laims are interpreted with an eye toward giving effect to all 12 terms in the claim.”). And as Intel points out, “claim 5, which depends on claim 4, specifically 13 recites a ‘VSS switch’ as part of the ‘reference power converter’” which “further confirm[s] that 14 ‘VSS’ in claim 4 is limiting.” Intel Reply at 11. 15 VLSI’s case law does not suggest a different outcome. In NXP USA, Inc. v. Impinj, Inc., 16 the court construed the term “specific useful data (n×UDB)” (where UDB means useful data 17 blocks, n is the number of UDB, and n and UDB are multiplied together in the parenthetical) to 18 mean “some, but not all, useful data (UD).” 2022 WL 16716226, at *8. VLSI contends that the 19 NXP court found that the parenthetical “referred to examples . . . that are labeled . . . in the 20 specification and figures, without incorporating every feature of these examples into the claims.” 21 VLSI Opp. at 11–12. The Court disagrees. In NXP, Impinj argued that “the inclusion of 22 ‘(n×UDB)’ in the claims refers only to specific useful data transmitted in response to a request.” 23 2022 WL 16716226, at *9. But the court disagreed with Impinj, instead finding 1) it was “unclear 24 whether the patent defines ‘n×UDB’ to refer only to requested data” and 2) the term “n×UDB” 25 was used inconsistently throughout the patent. Id. at *10. The issue before this Court is 26 distinguishable. Unlike the term “n×UDB,” which was not fully defined and was used 27 inconsistently, here, the term “VSS” has clear meaning to both parties (Mangione-Smith Dep. 28 139:3–141:6; Intel Reply at 7) and is used consistently throughout the patent (’922 Patent at 5:11, 31 1 2 3 5:13, 5:16–17, 6:59, 6:64–65, 7:52, 8:45, 8:52). VLSI’s argument that “VSS” is a reference character is also unavailing. MPEP 608.01(m) provides (emphasis added): 4 When there are drawings, there shall be a brief description of the several views of the drawings and the detailed description of the invention shall refer to the different views by specifying the numbers of the figures, and to the different parts by use of reference letters or numerals (preferably the latter). 5 United States District Court Northern District of California 6 7 VLSI contends that “VSS” is a reference character. But “VSS” is a well-known term with an 8 understood meaning in the field, as Dr. Mangione-Smith acknowledges. Mangione-Smith Dep. 9 139:3–141:6. To use a well-known term discussed throughout the specification as a reference 10 character would be an implausibly irresponsible way to label a circuit or prosecute a patent. Core 11 Wireless and Hochstein are thus of no use to the Court because both concerned “reference 12 characters” or “reference numbers” used to identify elements in patent drawings. Core Wireless, 13 2015 WL 6956722, at *5, *7 (addressing whether “reference numbers” were limiting); Hochstein, 14 2009 WL 1838975, at *12–16 (addressing whether reference characters “L1, L2” in the 15 parenthetical “communication couplers (L1, L2)” were limiting). 16 17 18 19 Thus, the Court finds that the parenthetical term “(VSS)” limits the term “reference signal.” b. Infringement Under This Claim Construction The issue now is whether this construction dooms VLSI’s theory of infringement. Intel 20 argues that Dr. Mangione-Smith’s opinion that VDD and VSS are the same is problematic 21 because, according to Intel, he admitted during deposition that VSS and VDD must be different. 22 Intel Mot. at 9; Mangione-Smith Dep. 132:8–134:12, 135:6–11, 136:22–138:3, 172:23–173:6. 23 Intel further argues that VDD and VSS cannot be the same because the ’922 Patent describes VDD 24 and VSS as different voltage signals. Intel Mot. at 9; ’922 Patent at 2:16–30, 2:44–53, 5:63–67, 25 6:52–53, 8:26–53 (“external supply signal, VDD”); ’922 Patent at 5:10–17, 6:64–65, 7:50–54, 26 8:26–53 (“reference signal, VSS”); ’922 Patent, Figs. 1–6 (all depicting “VDD” as a separate 27 voltage signal at the header of the power island and “VSS” as the voltage signal at the footer of the 28 power island); id., Fig. 4 (showing VDD as “1.0V” and VSS as “0.0V”); Apsel Rebuttal Report ¶¶ 32 1 144–167. In response, VLSI does not back away from its theory that VDD and VSS are the same United States District Court Northern District of California 2 3 voltage signal. VLSI Opp. at 9–11. Instead, VLSI argues that nothing in the claims prevents the 4 “supply signal” from being the “reference signal.” VLSI Mot. at 9–10 (citing Powell v. Home 5 Depot U.S.A., Inc., 663 F.3d 1221, 1231–32 (Fed. Cir. 2011)). VLSI further argues that Dr. 6 Mangione-Smith left open in his deposition the possibility that VDD and VSS are the same 7 voltage signal. See e.g., id. (“that a POSA would ‘generally’ understand a voltage labeled VSS to 8 ‘likely not to be a higher voltage’ than a voltage labeled VDD, which does not prevent them from 9 being equal.”) (quoting Mangione-Smith Dep. 135:6–11). VLSI also points to lengthy excerpts of 10 the Mangione-Smith Suppl. Report (“identifying these signals”) and Mangione-Smith Reply 11 Report, which “respond[s] to Intel’s supply and reference signal arguments.” VLSI Opp. at 10–11 12 (citing Mangione-Smith Suppl. Report ¶¶ 196–203, 230–34, ECF No. 579-12 (Mangione-Smith 13 Reply Report) ¶¶ 133–65). The Court agrees with Intel. As an initial matter, the Court finds that the parties agree that 14 15 Dr. Mangione-Smith’s theory of infringement identifies a signal called VCCIN as meeting both 16 the VDD and VSS limitations. See Mangione-Smith Suppl. Report ¶ 197 (“Intel documents show, 17 for example, that the voltage supply to an internal voltage regulator, as denoted in some 18 documents by symbols such as ‘Vccin,’ ‘Vcc,’ and ‘Vin’, is an example of an external supply 19 signal (VDD)”) (emphasis added); id. ¶ 232 (“an Intel presentation on FIVR depicts a block that receives a signal ‘Vin’ and produces an input to a ‘DAC’ block. This input 20 21 to the 22 a reference signal VSS.”) (emphasis added); Intel Mot. at 8; VLSI Opp. at 11. 23 is an example of a reference line, and the signal ‘Vin’ is an example of VLSI’s argument that the supply signal (VDD) and the reference signal (VSS) can be the 24 same signal fails. VLSI points to additional examples and embodiments in “other parts of the 25 specification not cited by Intel [that] contemplate signals provided by multiple sources in some 26 embodiments and by a common source in others.” VLSI Opp. at 10; see, e.g., ’922 Patent at 4:46– 27 57 (embodiments where “supply signals” are generated by three sources or one source), 5:4–17 28 (stating that circuits may connect to “separate nodes of the same reference signal,” “the same node 33 1 of a single reference signal,” and “two or more distinct reference sources”). VLSI also claims that 2 “there are embodiments in which voltages that are depicted as distinct in one of the patent’s 3 figures are nevertheless the same.” VLSI Opp. at 10; ’922 Patent at 4:49–55 (controls depicted as 4 providing “different” supply signals in Figure 1 may in “other embodiments” provide signals 5 “with the same or similar supply voltages”). These citations to the patent amount to little more 6 than attorney argument and vague speculation, thus the Court finds that they are not probative 7 evidence of infringement. 8 9 10 United States District Court Northern District of California 11 12 13 14 15 16 VLSI’s argument that Dr. Mangione-Smith opined that VSS and VDD could be the same voltage signal also fails. Dr. Mangione-Smith testified at his deposition that VDD and VSS are generally different voltages: Q. Okay. Now, let’s look back at the ’922 Patent, at figure 2 again. There’s a reference that we discussed earlier to VDD at the top; right? A. Yes. Q. And there’s a reference to VSS at the bottom; correct? A. Yes, that’s correct. Q. And those are using two different labels for two voltages; correct? A. Yes, that’s correct. Q. You would expect them to be distinct; correct? A. Yes. Generally, unless, you know, the one exception would be if the VDD had a power gate that was turned off. But during operation, I would certainly expect them to be different voltages. 17 Mangione-Smith Dep. 132:8–24 (emphasis added). Dr. Mangione-Smith also testified that the 18 difference between VDD and VSS is generally defined as the voltage across a circuit: 19 20 21 22 23 24 25 A. . . . Yeah, VDD is generally defined, relative to VSS. Q. And what do you mean by, “VDD is defined generally, relative to VSS”? A. Well, VDD is providing a voltage. What voltage? Voltage is always relative. So you know, if we’ve got something that we call 0 volts and we measure that this thing is 2 volts higher, we would call VDD 2 volts. That doesn’t mean, in any absolute sense, there’s 0 volts and 2 volts. It’s all relative. Q. So VDD minus VSS is the voltage across the circuit; right? A. In general, yeah. As in most – you know, if a person of ordinary skill in the art saw a circuit with VDD and VSS, I think that they would go in with the assumptions that that was the voltage across the circuit, the difference between the two. 26 Mangione-Smith Dep. 137:2–20. VLSI tries to make the most of these statements by claiming 27 that Dr. Mangione-Smith technically left open the possibility of VSS and VDD being the same. 28 VLSI Opp. at 11 (“a POSA would ‘generally’ understand a voltage labeled VSS to ‘likely not to 34 1 be a higher voltage’ than a voltage labeled VDD, which does not prevent them from being equal”) 2 (quoting Mangione-Smith Dep. at 135:6–11). But this stretches his testimony too far. Dr. 3 Mangione-Smith only presents one example where VDD and VSS would be the same, if “VDD 4 had a power gate that was turned off” and he does not claim this situation as part of his theory of 5 infringement. Mangione-Smith Dep. 132:8–24. Rather, Dr. Mangione-Smith states quite clearly 6 that “during operation,” he “would certainly expect [VSS and VDD] to be different voltages.” Id. United States District Court Northern District of California 7 VLSI’s citation to Powell for the prospect that “the same features in the accused product 8 satisfied two separately recited elements” also fails. VLSI Opp. at 10 (citing Powell, 663 F.3d 9 1221, 1231–32). In Powell, the Federal Circuit cited to a patent’s specification for evidence that 10 one component could meet two limitations. 663 F.3d at 1231 (“[T]he disclosure in the 11 specification cuts against Home Depot’s argument that the ‘cutting box’ and ‘dust collection 12 structure’ must be separate components . . . . [The specification] does not suggest that the claim 13 terms require separate structure”). Here, VLSI points to no such evidence from the specification 14 or claims of the ’922 Patent. Instead, all evidence, including the testimony of VLSI’s own expert, 15 suggests that VDD and VSS must be different. 16 Furthermore, the Court finds no probative evidence in VLSI’s citations to the Mangione- 17 Smith reports. VLSI Opp. at 10–11 (citing Mangione-Smith Suppl. Report ¶¶ 196–203, 230–34, 18 ECF No. 579-12 (Mangione-Smith Reply Report) ¶¶ 133–65). The excerpts of Dr. Mangione 19 Smith’s supplemental report lay out only the infringement theory critiqued by Intel where VCCIN 20 is both VSS and VDD. Mangione-Smith Suppl. Report ¶¶ 197, 232. VLSI points to no evidence 21 of an alternative theory of infringement or an explanation that VSS and VDD can be the same 22 voltage signal. Dr. Mangione Smith’s reply report fares no better. The fifteen-page excerpt 23 provided by VLSI in its opposition papers takes issue with Intel expert Dr. Apsel’s claim 24 construction of VSS, but does not put forth any affirmative infringement theory where the 25 reference signal is VSS. See, e.g., ECF No. 579-12 (Mangione-Smith Reply Report) ¶ 135 (“Dr. 26 Apsel further states that the term reference as used in the ’922 Patent is always and consistently 27 used to mean VSS or ground . . . . I disagree.”) (citations and quotations omitted); id. ¶ 140 (“I 28 disagree with Dr. Apsel that the examples she cites provide support for her conclusions about the 35 1 meanings of ‘VSS,’ ‘reference,’ and ‘ground.’”); id. ¶¶ 156–165 (opining that the term “VSS” in 2 claim 4 is not limiting because it is in parentheses). The reply report excerpt is of no use here 3 because it pertains to claim construction, which the Court addressed in the previous subsection. United States District Court Northern District of California 4 All evidence (other than attorney argument and vague speculation) suggests that VDD and 5 VSS are different voltage signals, which is at odds with Dr. Mangione-Smith’s infringement 6 theory that VCCIN satisfies both the VSS and VDD limitations. Mangione-Smith Suppl. Report 7 ¶¶ 197, 232. Furthermore, VLSI put forth no other theory of infringement in its opposition. Thus, 8 the Court finds that Intel has shown that an essential element of VLSI’s infringement claim is 9 missing, and that VLSI has therefore failed to put forth material evidence in support of a theory of 10 infringement. The Court finds as a matter of law that VLSI cannot prove that Intel infringes the 11 ’922 Patent, so Intel’s Motion for Summary Judgment of no infringement of the ’922 Patent is 12 granted. 13 3. Validity of the ’922 Patent 14 Intel further contends that the Asserted Claims of the ’922 Patent are invalid as indefinite 15 as a matter of law because the patent “fails to provide persons of ordinary skill with information 16 sufficient to determine with reasonable certainty when a component is a ‘power island’ and when 17 it is not.” Intel Mot. at 11. 18 “[A] patent is invalid for indefiniteness if its claims, read in light of the specification 19 delineating the patent, and the prosecution history, fail to inform, with reasonable certainty, those 20 skilled in the art about the scope of the invention.” Nautilus, Inc. v. Biosig Instruments, Inc., 572 21 U.S. 898, 901 (2014); see also Media Rights Techs., Inc. v. Capital One Fin. Corp., 800 F.3d 22 1366, 1371 (Fed. Cir. 2015) (“[A] claim is indefinite if its language might mean several different 23 things and no informed and confident choice is available among the contending definitions.”) 24 (citations and quotations omitted). 25 26 27 28 The Background section of the ’922 Patent describes a “power island” as a group of components with “similar” power requirements: One power management design approach combines components with similar power requirements into groups, which are referred to as power islands or, in some instances, voltage islands. All of the 36 components within a power island typically have similar power characteristics that are unique from the power characteristics of other power islands. 1 2 3 ’922 Patent at 1:29–35 (emphasis added). The two independent Asserted Claims of 4 the ’922 Patent (claim 1 and claim 17) contain language describing components of a 5 power island with power characteristics that are “different” or “partially different.” 6 Claim 1 reads: 7 A power island for a system-on-a-chip (SoC), the power island comprising: 8 9 a first segment comprising a hardware device, the first segment to operate the hardware device at first power characteristics indicative of at least a first voltage; 10 United States District Court Northern District of California 11 12 a second segment comprising scalable logic, the second segment to operate the scalable logic at second power characteristics indicative of at least a second voltage, wherein the second power characteristics of the scalable logic are different from the first power characteristics of the hardware device; . . . 13 14 15 ’922 Patent at 9:9–20 (claim 1) (emphasis added). Claim 17 reads: A method for making a power island for a system-on-a-chip (SoC), the method comprising: 16 17 18 19 20 21 coupling a memory device to a supply line of the power island, wherein the supply line is configured to receive an external supply signal (VDD) from an external power control to operate the memory device according to first power characteristics; coupling a supply power converter to the supply line of the power island, wherein the supply power converter is configured to change at least one power characteristic of the external supply signal to supply an internal supply signal (VDDi) to a logic module on the power island according to second power characteristics that are at least partially different from the first power characteristics; . . . 22 23 24 Id. at 11:41–12:13 (claim 17) (emphasis added). Intel argues that the claims are indefinite because they describe power islands with the 25 contradictory terms of degree “similar,” “different,” and “partially different.” Intel first argues 26 that the specification “suggests that the existence of a ‘power island’ turns on the degree of 27 similarity between the ‘power characteristics’ of components—without providing any information 28 about how to determine when a component is sufficiently ‘similar’ in that respect to qualify as a 37 1 ‘power island.’” Intel Mot. at 12. Intel then argues that the claim language of the Asserted Claims 2 “impos[es] another degree-based standard, but in the opposite direction—by requiring certain 3 components within the ‘power island’ to have ‘power characteristics’ that are ‘different’ (claim 1, 4 from which claims 4 and 5 depend) or “partially different” (claim 17, from which claim 18 5 depends) from the “power characteristics” of other components within the ‘power island.’” Id. 6 (citing ’922 Patent). Intel adds that first-named inventor David Evoy’s testimony shows that the 7 term is indefinite because he could not identify objective boundaries for the term “power island” 8 but instead “confirmed none exists.” Intel Mot. at 13. United States District Court Northern District of California 9 Intel cites three cases with indefiniteness arguments comparable to those in the instant 10 case. In Varian Med. Sys., Inc. v. ViewRay, Inc., the court found that a claim for a medical device 11 requiring “substantially the same” and “different” cross sections was indefinite where “the 12 specification does not contain objective guidance to inform a POSITA regarding what cross 13 sections would qualify as ‘substantially same’ or ‘different.’” No. 19-cv-05697-SI, 2020 WL 14 4260714, at *6–7 (N.D. Cal. July 24, 2020). In ACQIS LLC v. Alcatel-Lucent USA Inc., the court 15 found that the term “similar in design” in a computer system patent was indefinite where plaintiff 16 “was unable to articulate any point at which components or circuitry would cease to be ‘similar’” 17 and “the claims fail[ed] to ‘provide objective boundaries for those of skill in the art.’” No. 6:13- 18 cv-638, 2015 WL 1737853, at *10 (E.D. Tex. Apr. 13, 2015). And in Power Integrations, Inc. v. 19 ON Semiconductor Corp., the court found that a “moderate power level” in power supply circuit 20 patent was indefinite where the specification failed to “provide some meaningful way to determine 21 what the moderate value is.” No. 16-cv-06371-BLF, 2018 WL 5603631, at *20 (N.D. Cal. Oct. 22 26, 2018) 23 VLSI responds with several arguments. First, VLSI argues that “the preamble term ‘power 24 island’ is not a limitation in the asserted claims” because the term appears only in the preamble of 25 claim 1. VLSI Opp. at 12–13. Rather, VLSI asserts that its “expert confirms, a ‘power island’ in 26 the sense of claim 1 is simply a system having the components that are recited in the body of claim 27 1: a structurally complete invention.” Id. (citing ECF No. 617-11 (Mangione-Smith Reply Report) 28 ¶¶ 100–13). Second, VLSI contends that Intel’s arguments “erroneously presume that the claim 38 1 preambles incorporate aspects of the ‘Background’ section as limitations” and noted that none of 2 Intel’s cases address preamble language. Id. at 13. Third, VLSI argues that Intel waived its 3 indefiniteness argument. Id. Finally, VLSI counters Mr. Evoy’s deposition testimony about the 4 breadth of the term power island by countering that its own expert has shown that the accused 5 products contain “power islands” under the plain and ordinary meaning of the term. Id. at 12–13 6 (citing ECF No. 617-11 (Mangione-Smith Reply Report) ¶¶ 171–78). 7 8 one or more non-preamble limitations directed to ‘the power island.’” Intel Reply at 8–9. Intel 9 also points to evidence that it reserved its right at Markman to make an indefiniteness argument at 10 11 United States District Court Northern District of California Intel replies that the term “power island” is limiting because “every asserted claim contains summary judgment and disclosed indefiniteness theories in its contentions. Id. at 9. The Court first addresses VLSI’s waiver argument. Intel provides several examples in its 12 reply papers showing that it disclosed the indefiniteness argument currently before the Court. For 13 example, Intel stated in its Invalidity Contentions: 14 15 16 17 18 All asserted claims of the ’922 patent . . . are invalid under 35 U.S.C. 112. . . . For example, the specification states that “power islands” can mean “components with similar power requirements” and that power islands “typically have similar power characteristics that are unique from the power characteristics of other power islands” ’922 patent at 1:20–35. However, claim 1 and its dependents also require segments within the power island must have different power characteristics from one another. 19 ECF No. 710-10 (3/19/18 Contentions) at 1594–95; ECF No. 710-11 (1/26/22 Contentions) at 20 1377 (same); Apsel Report ¶ 1181; Apsel Reply Report ¶ 666. Furthermore, Intel stated in its 21 Markman briefing that “Intel may raise at a later time . . . such as in an authorized Motion for 22 Summary Judgment[] any indefiniteness arguments as to th[at] term[].” ECF No. 106. The Court 23 finds that Intel’s disclosures and explicit reservation of rights show that Intel did not waive its 24 indefiniteness argument. 25 VLSI’s argument that the term “power island” is not limiting also fails. Preamble 26 language is not limiting “where a patentee defines a structurally complete invention in the claim 27 body and uses the preamble only to state a purpose or intended use for the invention.” 28 Acceleration Bay, LLC v. Activision Blizzard Inc., 908 F.3d 765, 770 (Fed. Cir. 2018) (quoting 39 1 Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002)). But 2 “[w]hen limitations in the body of the claim rely upon and derive antecedent basis from the 3 preamble, then the preamble may act as a necessary component of the claimed invention.” Eaton 4 Corp. v. Rockwell Int’l Corp., 323 F.3d 1332, 1339 (Fed. Cir. 2003). Here, the remaining claims 5 rely on the antecedent basis from the preamble. See, e.g., ’922 Patent at 9:53 (claim 4) (“the 6 power island”), 12:7 (claim 17) (same). Thus, the Court finds that the term “power island” is 7 limiting. 8 United States District Court Northern District of California 9 Having found that Intel has not waived its indefiniteness argument and that the term “power island” is limiting, the Court turns to the substance of the parties’ indefiniteness 10 arguments. Again, the Court agrees with Intel. VLSI does not provide, and the Court cannot find, 11 any objective guidance or boundaries in the patent that persons of ordinary skill could use to 12 determine with reasonable certainty when “power characteristics” are “different” and “partially 13 different”—yet at the same time sufficiently “similar”—to be within the claimed “power island.” 14 Other than its preamble argument (VLSI Opp. at 13), which the Court has rejected, VLSI has 15 made no effort to distinguish Intel’s cases. The Court is particularly persuaded by Varian, where 16 the court found that claims describing cross-sections of “leaves” used in radiotherapy as 17 “substantially the same” and “different” were indefinite despite “some examples” in the 18 specification “of what could be considered ‘substantially same’ and ‘different’” and expert 19 testimony “that a 1-3 percent difference in leaf width would qualify as ‘substantially same’ while a 20 20-50% in leaf width would not” because the specification “[did] not disclose any dimensions, 21 angles, or position of radiation source.” 2020 WL 4260714, at *6–7. 22 Here, VLSI similarly points to nothing in the specification describing power characteristics 23 in a way that gives any objective meaning to the words “similar,” “different,” and “partially 24 different.” VLSI’s only purported evidence is eight paragraphs of the Mangione-Smith Reply 25 Report, where VLSI argues that its expert “has shown that the accused products contain ‘power 26 islands’ under the plain and ordinary meaning of the term.” VLSI Opp. at 15. Much of this 27 excerpt is concerned with which components belong in a power island, not the power 28 characteristics within the power island. See, e.g., Mangione-Smith Reply Report ¶ 171 (“To the 40 United States District Court Northern District of California 1 extent that Dr. Apsel believes that two components cannot be part of a ‘group of components with 2 similar power requirements’ if they are supplied by different FIVRs, I disagree”); id. at ¶ 175 (“I 3 do not understand how evidence that might be cited in support of a conclusion that the accused 4 PCU, L3 cache/LLC, and cores are part of the same ‘power island’ constitutes a ‘theory’ that 5 excludes other things . . . from being parts of the same ‘power island.’”) (emphasis in original). 6 The final paragraph discusses power characteristics and lists the terms “similar,” “different,” and 7 “partially different,” but does not attempt to define their boundaries. Id. at ¶ 178 (“the definition 8 of power island does not preclude groups of components with partially different or different power 9 characteristics if those characteristics would be considered similar by one of ordinary skill in the 10 art.”) (quoting IPR2018-01144, Paper No. 32 (Final Written Decision) at 77, 79). Contrary to 11 what VLSI’s briefing claims, the Court cannot identify any explanation from Dr. Mangione- 12 Smith’s Reply Report about how the power island is understood under the plain and ordinary 13 meaning of the term. More importantly, the report supplies no evidence of objective boundaries or 14 guidance on the scope of the power characteristics within a power island that explains what 15 “similar,” “different,” and “partially different” mean. Thus, the Court finds that a person of 16 ordinary skill, looking to the specification and the prosecution history, could not with reasonable 17 certainty determine the scope of the claim. Nautilus, 572 U.S. at 910. 18 The Court is also persuaded by testimony of the first-named inventor, David Evoy. 19 “[I]nventor testimony” is “evidence [that] may be helpful to explain . . . the meaning of technical 20 terms, and terms of art.” Markman v. Westview Instruments, Inc., 52 F.3d 967, 980 (Fed. Cir. 21 1995), aff’d, 517 U.S. 370 (1996). Mr. Evoy testified that the meaning of “power island” may be 22 “a quite fluid definition,” Evoy Dep. 96:4–17, “could change depending on the context of a 23 meeting and who was there,” id. at 97:23–98:1, and “might even depend [on] who is sitting across 24 the table from me,” id. at 96:14–17. So boundless was the term to him that he could not say 25 whether “[w]ithin the context of power management, maybe Manhattan could be a power island.” 26 Id. at 82:22–24. While the deposition testimony is secondary in the Court’s determination, the 27 Court finds that Mr. Evoy’s inability to identify objective boundaries for the term “power island” 28 further suggests that the claims are indefinite. 41 1 Where Intel has put forth evidence from the specification and the inventor that the term 2 “power island” is indefinite, VLSI has put forth no material evidence to the contrary. Intel has 3 shown, as a matter of law, that the ’922 Patent is indefinite. Thus, Intel’s Motion for Summary 4 Judgment that the ’922 Patent is invalid as indefinite is granted. 5 4. Infringement of the ’806 Patent United States District Court Northern District of California 6 VLSI accuses Intel of infringing claims 11, 12, 13, and 15 of the ’806 Patent. Intel Mot. at 7 13. The claims all require a “first memory” and a “second memory,” and two different modes of 8 operation, “a first mode of operation” and “a second mode of operation.” ’806 Patent at 10:31–57. 9 The Court construed “second mode of operation” to require that, “when in the second mode of 10 operation, both the voltage provided to the first memory and the voltage provided to the second 11 memory must be lower than the minimum operating voltage of the first memory.” Markman 12 Order at 7. 13 14 Dr. Conte describes VLSI’s theory of infringement. According to Dr. Conte, a circuit component called a sleep transistor . For the first mode of 15 16 operation, when a memory is being read from or written to, the sleep transistor 17 Conte Report ¶¶ 807, 874; ECF No. 678-14 at 2. For the second mode of 18 19 operation, when the memory is not being read from or written to, on the other hand, the sleep 20 transistor 21 22 23 Conte Report ¶¶ 806, 874; ECF No. 678-14 (Bendt Dep.) 76:13–77:11; ECF No. 678-5 (Conte 24 Dep.) 191:6–23. 25 Intel makes two arguments. First, Intel argues that “VLSI and Dr. Conte have failed to 26 identify any ‘minimum operating voltage’ for the data array memory in Intel’s products accused as 27 the claimed ‘first memory.’” Intel Mot. at 15. Intel further contends that “Dr. Conte’s opinion 28 that a minimum operating voltage exists for each of the numerous individual bitcells within the 42 1 2 VLSI responds that Dr. Conte concluded that “when the accused products are in the second 3 mode of operation, ‘the voltages supplied to the LLC data array [(the first memory of claim 11)] 4 and the DCU state arrays [(the second memory of claim 11)], respectively, are lower than the 5 minimum necessary for the first mode of operation.’” VLSI Opp. at 15 (citing Conte Report ¶ 6 941). VLSI argues that there is no need to quantify the minimum operating voltage to meet either 7 the claims or the Court’s construction. Id. 8 United States District Court Northern District of California accused data array memory” does not address the claim limitation. Id. On this first point, the Court agrees with VLSI. The Court construed the term “second 9 mode of operation” to have its “[p]lain and ordinary meaning, which includes the requirement of 10 claim 11 that when in the second mode of operation the voltage(s) supplied to the first and second 11 memory, respectively, must be lower than the minimum necessary for the first mode of operation.” 12 Markman Order at 6. A recitation of specific voltages is not required to meet the claim limitations 13 as long as the voltage “when in the second mode of operation” is lower than “the minimum 14 necessary for the first mode of operation.” Id. 15 Second, Intel argues that Dr. Conte’s Report does not show the difference in voltages 16 because it improperly focuses on the minimum operating voltages of bitcells. Intel Mot. at 14–15. 17 Intel argues that “Dr. Conte does not allege that the purported minimum operating voltage of a 18 bitcell is the same as the minimum operating voltage of the data array memory; instead, he 19 concedes that the data array memory can operate at voltages “even below” the bitcells’ minimum 20 operating voltage.” Id. at 14 (citing Conte Reply Report ¶ 758); see also ECF No. 579-5 (Conte 21 Dep.) 224:15–18 (“[T]he array can have a different, slightly different minimum operating voltage 22 from the first memory cell topology or the second memory cell topology of the memory cells.”). 23 VLSI responds with evidence that in both modes of operation, the DCU state array, the 24 “second memory” of claim 11, is able to read and write, but when in the second mode of 25 operation, the DCU state array receives a voltage lower than the minimum required to read and 26 write the LLC memory array. Conte Report ¶¶ 940–51; Conte Reply Report ¶¶ 742–49. 27 The Court finds the Dr. Conte’s report provides sufficient evidence to survive summary 28 judgment. Dr. Conte concludes that “the voltages supplied to the LLC data array and the DCU 43 1 state arrays, respectively, are lower than the minimum necessary for the first mode of operation” 2 because “the minimum operating voltage of the DCU state array bitcells is lower than the 3 minimum operating voltage of the LLC data array in each of the ’806 Accused Products.” Conte 4 Report ¶ 943. Drawing all inferences in VLSI’s favor, the Court finds that Dr. Conte’s reports and 5 deposition testimony create a genuine dispute of material fact as to whether Intel infringes the 6 ’806 Patent. Thus, Intel’s Motion for Summary Judgment of no infringement of the ’806 Patent is 7 denied. United States District Court Northern District of California 8 5. Infringement of the ’672 Patent 9 The sole asserted claim of the ’672 Patent is directed to a chip-assembly process that 10 includes a step whereby a “solder composition is provided as a fluid layer on the underbump 11 metallization, which layer makes a contact angle of less than 90° with the underbump 12 metallization.” ’672 Patent at claim 2. 13 VLSI accuses two Intel assembly processes, the relevant steps of which are undisputed: (1) 14 a “Current Process” (used since 15 onto what VLSI accused as the claimed “underbump metallization”; and (2) a “Discontinued 16 Process” (not used since 17 18 19 20 21 ), in which Intel ), in which Intel onto the accused underbump metallization. ECF No. 579-15 (“Neikirk Report”) ¶¶ 140, 148–49, 153; Intel Mot. at 16. Intel argues that the Court should grant summary judgment of no infringement “because there is no genuine dispute of material fact that (1) in the Current Process, solder is ‘provided’ , and (2) in the Discontinued Process, the contact angle between the 22 solder composition and the accused underbump metallization was not ‘less than 90°.’” Intel Mot. 23 at 15–16. The Court addresses the two processes in turn. 24 25 a. Current Process The Current Process (used since ), uses . 26 Intel Mot. at 16. Intel argues that this 27 expert Dr. Dan P. Neikirk is not accusing 28 layer.” ECF No. 579-16 (“Neikirk Dep.”) 151:3–52:3. Thus, says Intel, the Current Process does , and that VLSI as “provid[ing] solder as a fluid 44 1 not infringe “because claim 2 requires that the solder composition be ‘provided as a fluid layer,’ 2 and because it is undisputed that [the Current Process] instead 3 Mot. at 16–17. United States District Court Northern District of California 4 .” Intel VLSI disputes Intel’s definition of the term “provided.” VLSI Opp. at 19. VLSI cites to 5 testimony of its expert Dr. Neikirk, who said that Intel “does not explain why, if ‘providing’ a 6 solder composition had been intended to be limited to initial application of solder, the drafters of 7 the ’672 Patent chose to use the broader term ‘providing’ instead, and to make no reference to the 8 step being ‘initial’ or being onto a surface that previously was solder-free.” ECF No. 678-19 9 (“Neikirk Reply Report”) ¶ 58. VLSI argues that contrary to Intel’s assertion, the ’672 Patent 10 specifically emphasizes that “the solder [] can be applied in different manners.” ’672 Patent at 11 2:7–8. Dr. Neikirk further opines that a POSA would understand the plain meaning of “provide” 12 to encompass making available or supplying. See, e.g., ECF No. 677-23 (Merriam-Webster 13 definitions of provided) (“to supply or make available; to make something available to”); ECF No. 14 677-24 (Dictionary.com definitions of provided) (“to make available”); ECF No. 677-25 (Collins 15 dictionary definitions of provided) (“to make available; supply”); Neikirk Reply Report ¶ 57. 16 The Court has not construed the terms “provided” or “provided as,” and the Parties’ have 17 not provided sufficient briefing for the Court to construe the claims here. As such, the Court 18 applies VLSI’s construction for summary judgment only. Dr. Neikirk has testified that the 19 “current process involves fluid solder attaching to the accused underbump metallizations . . . 20 happens 21 .” Neikirk Report ¶¶ 204, 247 (citing witness testimony). 22 Given VLSI’s construction, Dr. Neikirk’s testimony creates a genuine dispute of material fact as to 23 whether the Current Process infringes the ’672 Patent. 24 b. Discontinued Process 25 The Discontinued Process (not used since 26 ), requires onto the accused underbump metallization. Neikirk 27 Report ¶¶ 140, 148–49, 153. Intel argues that the Discontinued Process does not infringe claim 2 28 because “VLSI has no evidence that any contact angle between 45 and the accused 1 underbump metallization is less than 90°, as required by claim 2” nor has VLSI “identified any 2 measurement of any contact angle in any Intel accused product.” Intel Mot. at 17. VLSI responds with “extensive expert evidence” that the angle is less than 90°. VLSI 3 4 Opp. at 19 (citing Neikirk Report ¶¶ 249–57, Neikirk Reply Report ¶¶ 59–62). VLSI also cites to 5 documents and images suggesting that 6 Neikirk Report ¶¶ 252–55 (collecting Intel evidence). The Court finds that VLSI’s evidence creates a genuine dispute of material fact as to 7 8 whether the Discontinued Process infringes the ’672 Patent. Thus, Intel’s Motion for Summary 9 Judgment of no infringement of the ’672 Patent is denied. 10 6. License Defense As discussed at Section III.A.1, the Court will issue a supplemental order regarding Intel’s 11 United States District Court Northern District of California . See Neikirk Reply Report ¶ 61; 12 license defense. 13 7. Willful Infringement, Indirect Infringement, and Enhanced Damages 14 Intel seeks summary judgment that any infringement was not willful or indirect because it 15 had no knowledge of the Asserted Patents, much less any knowledge of infringement. Indirect and willful infringement both require proof, for each asserted patent, that the 16 17 defendant knew or should have known (1) of the patent, and (2) that it was infringing the patent. 18 See Commil USA, LLC v. Cisco Sys., Inc., 575 U.S. 632, 639 (2015) (indirect infringement 19 “requires knowledge of the patent in suit and knowledge of patent infringement”); Arctic Cat Inc. 20 v. Bombardier Recreational Prods. Inc., 876 F.3d 1350, 1371 (Fed. Cir. 2017) (same for willful 21 infringement); Sonos, Inc. v. Google LLC, 591 F. Supp. 3d 638, 647 (N.D. Cal. 2022) (“Like 22 willful infringement, both forms of indirect infringement—induced and contributory 23 infringement—require knowledge of the patent and knowledge of infringement.”). There is no 24 “per se rule” under which district courts evaluate willfulness contentions; rather, the factfinder 25 must look to the “‘totality of the circumstances presented in the case.’” WCM Industries v. IPS 26 Corp., 721 F. App’x 959, 970 (Fed. Cir. 2018) (quoting Shiley, Inc. v. Bentley Labs., Inc., 794 27 F.2d 1561, 1568 (Fed. Cir. 1986)). 28 \\ 46 1 2 Some evidence of pre-suit knowledge put forth by VLSI pertains to all four of the Asserted 3 Patents, and the remaining evidence pertains only to the ’836 Patent. The Court first considers 4 evidence pertaining to all the Asserted Patents to make a determination for the ’806, ’922, and 5 ’672 Patents, then the Court considers additional evidence pertaining only to the ’836 Patent. 6 7 United States District Court Northern District of California a. Pre-Suit Knowledge i. ’806, ’922, and ’672 Patents Intel argues that for three of the asserted patents (the ’806, ’922, and ’672 Patents), VLSI 8 failed even to allege pre-suit knowledge by Intel in its complaint, interrogatory responses, or 9 contentions. Intel Mot. at 21–22; Compl. ¶¶ 47–49, 92–94, 120–22; ECF No. 580-41 (VLSI’s 10 Supplemental Response to Intel’s 3rd Set of Interrogatories, “Interrog. Resp.”) at 8–10; ECF No. 11 407-2 (VLSI’s Second Amend. Infringement Contentions) at 15–17; ECF No. 477-3 (VLSI’s Fifth 12 Suppl. Damages Contentions) at 216–218. 13 VLSI does not address Intel’s waiver argument, but instead responds with evidence that 14 purportedly shows that “Intel regularly monitors competitors’ (including NXP’s) activities, and 15 has acknowledged its competitors have patents covering similar products.” VLSI Opp. at 23; see, 16 e.g., ECF No. 677-28 (“Intel 2012 10-K”) at 17 (“Established competitors . . . as well as 17 companies that purchase and enforce patents and other IP, may already have patents covering 18 similar products.”); ECF No. 677-29 (“Intel Datasheet”) at -574 (“[T]he I2C bus/protocol may 19 require licenses from various entities, including NXP[.]”). VLSI also cites to evidence that “Intel 20 has a policy discouraging engineers from looking at third-party patents” in support of a willful 21 blindness theory including deposition testimony by Intel engineers and a 2006 book written by a 22 former Intel executive. VLSI Opp. at 23–24 (citing ECF No. 678-10 (“Therien 30(b)(6) Dep.”) 23 394:20–396:21, ECF No. 678-21 (“Chen Dep.”) 12:10–13:11, ECF No. 677-32 (“The Pentium 24 Chronicles”) at 161 & n.3). 25 Intel replies that VLSI’s argument that Intel monitors competitors “is (1) waived because 26 VLSI did not raise it in its complaint or contentions, and (2) irrelevant and misleading given that 27 VLSI admits that it has not identified any competitor products that supposedly practice the 28 asserted patents, including those of NXP.” Intel Reply at 14. Intel adds that its “engineers merely 47 1 explained their practice not to look at others’ patents (to avoid being ‘influenced’), and instead 2 focused on their own ‘innovations.’” Id. at 14–15 (citing Chen Dep. 12:10–13:11, Therien 3 30(b)(6) Dep. 394:20–396:21). 4 5 waived any argument that Intel had either knowledge of or knowledge of infringement of the ’806, 6 ’922, and ’672 Patents. Intel’s Interrogatory No. 19 states: 7 8 9 United States District Court Northern District of California As an initial matter, the Court agrees with Intel that VLSI failed to disclose and has thus State the facts and Identify all Documents on which VLSI bases its allegation that Intel has willfully infringed the Asserted Patents, including by Identifying each instance in which VLSI has given notice to Intel of any alleged infringement and the specific content of such notice. 10 Interrog. Resp. at 7–8. VLSI’s response, dated February 24, 2023, includes several general 11 allegations pertaining to the Asserted Patents. See, e.g., id. at 8 (“Intel has willfully infringed the 12 Asserted Patents and continues to willfully infringe them. VLSI expects to seek enhanced 13 damages as a result of the totality of the circumstances, including, among other things, Intel’s 14 willful infringement of the Asserted Patents.”). Of the four remaining Asserted Patents, the only 15 specific fact or document disclosed pertains to the ’836 Patent, which Intel cited “during the 16 prosecution of U.S. Patent No. 9,317,342” and “U.S. Patent No. 9,582,287.” Id. at 10; ’342 File 17 History. VLSI made no disclosure of the Intel 2012 10-K, the Intel Datasheet, or the book The 18 Pentium Chronicles, and did not cite to deposition evidence despite both depositions being taken 19 before VLSI’s response. Therien 30(b)(6) Dep. (taken on January 27, 2023); Chen Dep. (taken on 20 February 8, 2023); VLSI’s Supplemental Response to Intel’s 3rd Set of Interrogatories (signed on 21 February 24, 2023). Thus, the Court finds that VLSI has waived any argument related to 22 knowledge of or knowledge of infringement of the ’806, ’922, and ’672 Patents. 23 Even if VLSI’s evidence pertaining to the Asserted Patents is not waived, the evidence is 24 not significantly probative, and thus does not create a genuine dispute of material fact in support 25 of pre-suit willful or indirect infringement of the Asserted Patents. The Court addresses VLSI’s 26 evidence: the Intel 2012 10-K, the Intel Datasheet, and the depositions and book (the Court 27 addresses evidence specific to the ’836 Patent in the next subsection). 28 The first piece of evidence is the Intel 2012 10-K for the end of fiscal year 2012, which 48 1 2 3 4 United States District Court Northern District of California 5 states: Established competitors in existing and new industries, as well as companies that purchase and enforce patents and other IP, may already have patents covering similar products. There is no assurance that we will be able to obtain patents covering our own products, or that we will be able to obtain licenses from other companies on favorable terms or at all. 6 Intel 2012 10-K at 17. The Court finds that this disclosure is not probative evidence of knowledge 7 of the Asserted Patents. This is an ordinary corporate disclosure warning investors of the risks of 8 patent litigation. If Intel had not made this disclosure, it could just as easily face securities 9 litigation for failing to warn investors of the ever-present risk of patent litigation. And without 10 any specific mention of the Asserted Patents, or any connection or mention of the accused 11 technology, the Intel 2012 10-K is not material evidence of knowledge of the Asserted Patents, 12 much less knowledge of infringement of the Asserted Patents. 13 VLSI’s second piece of evidence is an Intel Datasheet, which states, “I2C ls a two-wire 14 communications bus/protocol developed by NXP. SMBus is a subset of the I2C bus/protocol and 15 was developed by Intel. Implementations of the I2C bus/protocol may require licenses from 16 various entities, including NXP Semiconductors N.V.” Intel Datasheet at 89607DOC00025574. 17 The Court finds that this is evidence of Intel’s general knowledge of the NXP patent portfolio and 18 knowledge of a risk of infringement of the NXP patent portfolio. But without any specific 19 mention of the Asserted Patents, or any connection between the technology described in the 20 datasheet and the accused technology, the Intel Datasheet is not material evidence of knowledge of 21 infringement of the Asserted Patents . 22 VLSI’s final set of evidence involves its claim that Intel is “willfully blind to risks of 23 patent infringement.” VLSI Opp. at 23. As an initial matter, the Court is concerned that this 24 willful blindness theory is at odds with the theory VLSI puts forth ten lines earlier in its brief that 25 “Intel regularly monitors competitors’ (including NXP’s) activities.” Id. 26 Potential contradictions aside, the deposition and book excerpt are not material evidence of 27 a corporate culture of willful blindness. For example, Tim Chen stated in his deposition that he is 28 “not aware of any policy” at Intel not to look at patents of other companies. Chen Dep. 12:10– 49 1 13:11. In his deposition, Guy Therien states that it is discouraged, but “not a prohibited policy” to 2 look at other patents. Therien 30(b)(6) Dep. 394:20–396:21. Therien explains: 3 4 5 6 7 8 United States District Court Northern District of California 9 Generally, it's discouraged by Intel for their technical folks to look at other companies' patents, but it's not a prohibited policy. Like, they say that you can obviously look at it. It's, you know, any kind of offense to Intel's rules. So there's times when you'll see something come up from a colleague where they'll say, hey, look at this patent. You know, we already have a patent on that. Don't you think -- you know, things like that. So there will be that kind of discussion, especially when you have a lot of patents. And then there also will be times when counsel will bring specific patents to my attention to see if I'm -- of a consultive nature to see if --you know, some conversation about it. So those are the situations where I would see patents from other companies. 10 Id. 394:20–395:12. The Court finds that this evidence does not support VLSI’s theory of willful 11 blindness because both engineers testified that Intel has no policy restricting its engineers from 12 looking at other companies’ patents. 13 As a third piece of evidence of willful blindness, VLSI cites the 2006 book The Pentium 14 Chronicles, written by Robert Colwell, Intel’s former chief architect. The cited footnote states, “It 15 is common practice in the industry to instruct engineers never to read the patents of other 16 companies, a direction they universally comply with most happily. This helps avoid possible 17 triple damages for ‘willful infringement’ if one’s company is ever found to be infringing on 18 another’s patent.” The Pentium Chronicles. The Court finds that this citation is not material 19 evidence in support of VLSI’s willful infringement allegation. First, the book was published in 20 2006 and VLSI presents no evidence that this “common practice” was ever an official policy at 21 Intel during the period of alleged infringement (in fact, the deposition testimony refutes any 22 inference that it was or still is). Furthermore, the book discusses potential patent infringement 23 related to the P6 microprocessor, and VLSI draws no connection from that technology to the 24 Asserted Patents or any accused technology. Finally, this is at best a general statement about 25 Colwell’s opinion about how the industry operates (circa 2006), not a clear statement that Intel 26 practiced this policy. As such, the Court finds that this is not material evidence of knowledge of 27 the Asserted Patents, knowledge of infringement of the Asserted Patents, or of willful blindness to 28 the Asserted Patents. 50 United States District Court Northern District of California 1 VLSI has put forth several pieces of evidence that are unrelated, tenuous, and not 2 significantly probative, perhaps in the hope that in combination they are equivalent to a single 3 piece of material evidence. But VLSI’s evidence is just as weak when viewed collectively under 4 the totality of the circumstances as it is individually. Only the Intel Datasheet is evidence of a 5 general knowledge of the NXP patent portfolio. And none of VLSI’s evidence indicates 6 knowledge of infringement of the Asserted Patents. 7 Having found that VLSI waived its argument that Intel had pre-suit knowledge and 8 knowledge of infringement of the ’806, ’922, and ’672 Patents, and that even if it hadn’t, VLSI’s 9 evidence does not create a genuine dispute of material fact as to whether Intel had pre-suit 10 knowledge of infringement of the ’806, ’922, and ’672 Patents, the Court finds as a matter of law 11 that VLSI cannot prove pre-suit willful or indirect infringement of the ’806, ’922, and ’672 Patents 12 by Intel. Thus, Intel’s Motion for Summary Judgment of no pre-suit willful or indirect 13 infringement of the ’806, ’922, and ’672 Patents is granted. 14 ii. ’836 Patent 15 For the reasons described above, the Intel 2012 10-K, the Intel Datasheet, and the 16 depositions and book excerpt similarly do not create a genuine dispute of material fact relating to 17 pre-suit willful or indirect infringement of the ’836 Patent. The Court addresses a final piece of 18 evidence directed towards only the ’836 Patent, a citation to the ’836 Patent in the prosecution of a 19 subsequent Intel patent. 20 Intel argues that “VLSI only has alleged pre-suit knowledge because ‘a patent examiner 21 cited the application that led to the ’836 Patent’ during prosecution of two other patents.” Intel 22 Mot. at 22 (citing Interrog. Resp. at 10). Intel argues that “the undisputed facts also demonstrate 23 that Intel did not have the requisite ‘knowledge of infringement.’” Intel Mot. at 23 (quoting Dali 24 Wireless, Inc. v. Corning Optical Commc’ns LLC, 638 F. Supp. 3d 1088, 1099 (N.D. Cal. 2022)). 25 VLSI responds with evidence that Intel was aware of the ’836 Patent because it cited the patent’s 26 application during prosecution. ECF No. 677-30 (“’342 File History”) at 8, 11, 13, 16–26. Intel 27 replies that VLSI has at most put forth evidence of “pre-suit knowledge of that patent” which it 28 argues is “irrelevant to VLSI’s burden to prove that Intel knew it infringed that patent.” Intel 51 1 2 The Court agrees with Intel. VLSI’s only authority on the matter found that “even 3 substantive references to patents in the alleged infringer’s patent prosecutions, without more, fail 4 to sufficiently allege knowledge of infringement.” MasterObjects, Inc. v. Amazon.com, Inc., No. 5 C 20-08103 WHA, 2021 WL 4685306, at *5 (N.D. Cal. Oct. 7, 2021). The Court follows 6 MasterObjects and concludes that the ’342 File History citation is at best evidence of knowledge 7 of the patent, but is not evidence of knowledge of infringement. 8 9 United States District Court Northern District of California Reply at 14. Having found that VLSI’s evidence does not create a genuine dispute of material fact as to whether Intel had pre-suit knowledge of infringement of the ’836 Patent, the Court finds as a 10 matter of law that VLSI cannot prove pre-suit willful or indirect infringement of the ’836 Patent 11 by Intel. Thus, Intel’s Motion for Summary Judgment of no pre-suit willful or indirect 12 infringement of the ’836 Patent is granted. 13 b. Post-Suit Knowledge 14 Intel also seeks summary judgment of no willful infringement and no indirect infringement 15 for the post-suit period. The issue here is not a dispute of evidence but rather of law. Intel argues 16 that a Complaint does not provide “requisite knowledge of the patents” required for willful or 17 indirect infringement. Intel Mot. at 22. VLSI responds that the Complaint, infringement 18 contentions, and refinements to those contentions provided further evidence of infringement and 19 cites to several cases where “post-filing conduct alone” support a theory of willful infringement. 20 VLSI Opp. at 24. 21 The cases cited by the parties show a split among district courts as to whether a complaint 22 provides adequate notice of willful and indirect infringement. Some courts have held that “a well- 23 pled, detailed complaint laying out a clear case of infringement could supply the knowledge (post- 24 complaint) required for willfulness once a defendant has had a reasonable period of time to 25 evaluate the complaint's contentions[.]” Dali, 638 F. Supp. 3d at 1099 (quotation omitted); see 26 also PersonalWeb Techs. LLC v. Int'l Bus. Machines Corp., No. 16-CV-01266-EJD, 2017 WL 27 2180980, at *21 (N.D. Cal. May 18, 2017) (finding that a dispute between the parties as to 28 whether the defendant’s “noninfringement and invalidity defenses . . . are reasonable” precluded a 52 United States District Court Northern District of California 1 finding at summary judgment of no willful infringement). Other courts have held (at the pleadings 2 stage) that a complaint alone is not sufficient to allege post-suit infringement. See Sonos, 591 F. 3 Supp. 3d at 648 (“[W]ithout a notice letter or circumstances like the examples described 4 previously, the complaint will generally not be adequate to serve as notice for either willful or 5 indirect infringement.”); Splunk Inc. v. Cribl, Inc., No. C22-07611 WHA, 2023 WL 2562875, at 6 *2–4 (N.D. Cal. Mar. 17, 2023) (similar); ZapFraud, Inc. v. Barracuda Networks, Inc., 528 F. 7 Supp. 3d 247, 250 (D. Del. 2021) (“[T]he complaint itself cannot be the source of the knowledge 8 required to sustain claims of induced infringement and willfulness-based enhanced damages.”); 9 VLSI Tech. LLC v. Intel Corp., 2019 WL 1349468, at *2 (D. Del. Mar. 26, 2019) (dismissing 10 willfulness-based enhanced damages claim where the plaintiff had alleged that the defendant 11 gained “knowledge of the [patent] at least since the filing of this complaint”). 12 On this, the Court agrees with Intel. “The purpose of a complaint is to obtain relief from 13 an existing claim and not to create a claim.” ZapFraud, 528 F. Supp. 3d at 251; Sonos, 591 F. 14 Supp. 3d at 648. Furthermore, because a complaint and infringement contentions are a necessary 15 part of patent litigation, a finding that they alone satisfy post-suit notice would invite claims of 16 willful infringement and indirect infringement into literally every patent suit. The Court has found 17 that VLSI’s only evidence of pre-suit infringement was knowledge of the ’836 Patent, and VLSI’s 18 only evidence of post-suit notice is its complaint and infringement contentions. Thus, VLSI’s 19 evidence does not create a genuine dispute of material fact that would preclude summary judgment 20 of no willful or indirect infringement. The Court finds as a matter of law that VLSI cannot prove 21 post-suit willful or indirect infringement of the Asserted Patents by Intel. Thus, Intel’s Motion for 22 Summary Judgment of no post-suit willful or indirect infringement is granted. 23 c. Enhanced Damages 24 Under 35 U.S.C. § 284, in a case of infringement, courts “may increase the damages up to 25 three times the amount found or assessed.” In Halo Elecs., Inc. v. Pulse Elecs., Inc., 579 U.S. 93 26 (2016), the Supreme Court held that § 284 “contains no explicit limit or condition” on when a 27 district court may award enhanced damages, but instead allows courts to “punish the full range of 28 culpable behavior.” Id. at 103, 106. This “sort of conduct warranting enhanced damages has been 53 United States District Court Northern District of California 1 variously described in our cases as willful, wanton, malicious, bad-faith, deliberate, consciously 2 wrongful, flagrant, or—indeed—characteristic of a pirate.” Id. at 103–04. Thus, under Halo, 3 willfulness is not a prerequisite to awarding enhanced damages, nor are enhanced damages 4 required upon a finding of willfulness. See id.; id. at 106 (“none of this is to say that enhanced 5 damages must follow a finding of egregious misconduct”). Instead, “courts should continue to 6 take into account the particular circumstances of each case.” Id. However, enhanced damages are 7 generally reserved for “egregious cases of misconduct beyond typical infringement,” such as those 8 “typified by willful misconduct.” Id. at 106, 110. To the extent that enhanced damages are based 9 at least in part on willfulness, “[k]nowledge of the patent alleged to be willfully infringed 10 continues to be a prerequisite to enhanced damages.” WBIP, LLC v. Kohler Co., 829 F.3d 1317, 11 1341 (Fed. Cir. 2016) (citing Halo, 579 U.S. at 104)); see also Finjan, Inc. v. Cisco Sys. Inc., 2017 12 WL 2462423, at *5 (N.D. Cal. June 7, 2017). Intel argues that “VLSI has offered no evidence that Intel’s conduct came even remotely 13 14 close to meeting that heightened standard” but instead that “the record shows nothing more than a 15 ‘garden-variety hard-fought patent case’ in which Intel has advanced non-frivolous defenses.” 16 Intel Mot. at 24 (citing Presidio Components, Inc. v. Am. Tech. Ceramics Corp., 875 F.3d 1369, 17 1382–83 (Fed. Cir. 2017)). In response, VLSI puts forth its evidence of willful infringement 18 (addressed above by the Court), but does not put forth any evidence of egregious conduct. VLSI 19 Opp. at 24–25. The Court agrees with Intel. As discussed above, the Court has found as a matter of law 20 21 that VLSI cannot prove that Intel willfully infringed the Asserted Patents. Furthermore, VLSI 22 puts forth no facts sufficient to show, and thus cannot prove as a matter of law, that Intel engaged 23 in egregious conduct based on Intel’s conduct up to this point. Intel’s Motion for Summary 24 Judgment of no enhanced damages is granted. If applicable, VLSI may reassert its claim of 25 egregious conduct supported by evidence relating to conduct occurring after VLSI filed its Motion 26 for Summary Judgment. 27 IV. 28 ORDER For the foregoing reasons, IT IS HEREBY ORDERED that: 54 1 1. VLSI’s Motion for Summary Judgment that Intel is barred under res judicata and collateral 2 estoppel from making its license defense is DENIED. The Court will issue a supplemental 3 order that addresses the parties’ remaining license defense arguments. 4 5 combinations – (2) Rakshani and Willingham; (3) Rakshani and Khellah; (4) Okada, 6 Zakel, and the Lee Book; and (6) Pahl, Shibata, and Basol – is GRANTED; it is DENIED 7 as to (1) Nehalem, Gunther, and Willingham and (5) Okada, the Lee Book, and the Intel 8 P1264 Package Process. The challenge to the Lee Book and AAPA is not properly before 9 the Court and thus there is no ruling on it. 10 United States District Court Northern District of California 2. VLSI’s Motion for Summary Judgment that Intel is estopped from using four obviousness 3. Intel’s Motion for Summary Judgment that it does not literally infringe the ’836 Patent 11 because it does not meet a temporal limitation is DENIED; Intel’s motion that it does not 12 infringe the ’836 Patent because testing is performed outside the country is GRANTED. 13 4. Intel’s Motion for Summary Judgment that it does not infringe the ’836 Patent under the 14 15 16 doctrine of equivalents is GRANTED. 5. Intel’s Motion for Summary Judgment that it does not infringe the ’922 Patent is GRANTED. 17 6. Intel’s Motion for Summary Judgment that the ’922 Patent is invalid is GRANTED. 18 7. Intel’s Motion for Summary Judgment that it does not infringe the ’806 Patent is DENIED. 19 8. Intel’s Motion for Summary Judgment that its manufacturing processes do not infringe the 20 21 22 23 ’672 Patent is DENIED. 9. Intel’s Motion for Summary Judgment that it did not willfully or indirectly infringe the Asserted Patents is GRANTED. 10. Intel’s Motion for Summary Judgment for no enhanced damages is GRANTED without 24 prejudice to reasserting a claim based on evidence postdating the filing of VLSI’s 25 opposition to this motion. 26 27 28 Dated: December 7, 2023 ______________________________________ BETH LABSON FREEMAN United States District Judge 55

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