HUGHES AIRCRAFT COMPANY v. General Instrument Corp., 374 F. Supp. 1166 (D. Del. 1974)

*1167 *1168 Thomas S. Lodge, Connolly, Bove & Lodge, Wilmington, Del., Dugald S. McDougall, McDougall, Hersh & Scott, Chicago, Ill., David F. Doody and Robert Thompson, Los Angeles, Cal., of counsel, for plaintiff.

Clair J. Killoran, Killoran & Van Brunt, Wilmington, Del., and Harold James, James & Franklin, New York City, for defendant.

Caleb M. WRIGHT, Senior District Judge.

This is a patent infringement action involving patent No. 3,544,399. The patent in suit discloses a method of making a silicon-gate field effect transistor. The patent was applied for on October 26, 1966 by Hans G. Dill, assignor of the plaintiff and was issued to the plaintiff as assignee on December 1, 1970.

The plaintiff and defendant are both Delaware corporations and this Court has jurisdiction of the subject matter under the provisions of 28 U.S.C. § 1338 and proper venue exists under 28 U.S.C. § 1400(b).

The complaint was filed May 12, 1972. The defendant answered denying infringement and averring that the patent in suit is invalid because the invention of the patent had been "made in this country by another who had not abandoned, suppressed or concealed it" before it was made by the plaintiff's patentee, Hans Dill.^[1] The defendant moved for a stay of the proceedings on the grounds that there was pending in the United States Patent Office the defendant's application in which the same invention as that in suit was being claimed and that the Patent Office had been asked to declare an interference between the defendant's application and the patent in suit.

This Court denied the defendant's motion for a stay of proceedings, ordered discovery be limited for the time being to the issue of priority of invention, and upon the completion of discovery on this issue ordered a separate trial.

The invention is a method of making semiconductor devices of a class known as silicon-gate field effect transistors in which the gate electrode is made of silicon rather than of metal as in the prior art (R. 52-60; PX 17 H-1H-3, I).

A field-effect transistor is a three-electrode electrical amplifier formed in a small body of monocrystalline silicon. Two electrodes, one designated as the "source" and the other as the "drain" are made by impregnating selected regions of the silicon body with impurity elements by a method known as "doping." The third electrode or the "gate" overlies the transistor body between the source and the drain, the gate, however, being insulated from the transistor body. Appropriate voltage is applied to the gate enabling current to flow from the source to the drain, and variations of the gate voltage produce corresponding variations in the current flowing from the source to the drain (R. 21-29, 48-50; PX 17 A, B).

*1169 Field-effect transistors made according to the prior art processes employed a gate electrode made of a thin layer of aluminum, insulated from the underlying silicon surface by an ultra-thin layer of silicon dioxide. The placement of the aluminum gate electrode in proper alignment with the source and drain was critical and difficult since the dimensions involved were very small and the permissible margin of error was minute (R. 49-54). In the process which is the subject matter of the patent in suit, the transistor silicon body is coated with a thin insulating layer of oxide, a gate electrode of a thin layer of polycrystalline silicon is then deposited on the oxide, the oxide layer is then etched away in the regions where the source and drain are to be formed, and the portions of the transistor body thus exposed are "doped" by diffusion at a temperature of approximately 1000° C. During the diffusion step the silicon gate electrode acts as a "mask" insuring that the source and drain electrodes are located precisely adjacent to the outer extremities of the gate electrode. This efficient method of alignment could not be employed with an aluminum gate electrode since it would melt and flow at the high temperature required for diffusion (R. 52-60; PX 17 H-1H-3, I).

The present phase of the litigation is governed by 35 U.S.C. § 102(g), which provides in part:

In determining priority of invention there shall be considered not only the respective dates of conception and reduction to practice of the invention, but also the reasonable diligence of one who was first to conceive and last to reduce to practice, from a time prior to conception by the other.

The Court will, therefore, first determine the respective dates of conception and reduction to practice by plaintiff and defendant.^[2]

The record is clear that Hans Dill, plaintiff's assignor, conceived of the silicon-gate invention in early May, 1966. Dill's discovery was contemporaneously recorded, beginning on May 1, in impressive detail, and his notebook entries were witnessed by his laboratory colleagues (PX 3, pp. 209-211, 215-216; R. 67-80). Plaintiff contends that Dill reduced his invention to practice in tests on May 12, 1966, or alternatively, in tests on October 18, 1966. Defendant contends, however, that Dill's invention was not reduced to practice before plaintiff's patent application was filed on October 26, 1966.

Dill testified that shortly after he conceived of the silicon-gate device, he asked two colleagues, Rowland and Knoll, to prepare actual transistors by the new method (R. 80-84). Dill testified that the first field-effect transistors made with his silicon-gate process were completed by May 12, 1966 and were tested by him on that day. This testimony is corroborated by photographs of the masks used to prepare these experimental devices (PX 3A, 3B; R. 83-89), and by Dill's contemporaneous notebook entry of the test results (PX 3, p. 215). However, plaintiff did not introduce into evidence any photographs of the actual silicon-gate devices, any reproductions of curves or test results for the devices, or any indication that witnesses other than Dill observed the tests.

Dill tested the experimental devices for transconductancethe amount of change in drain current resulting from a given change in gate voltage. The parties apparently agree that this test adequately measures the effectiveness of the device as a transistor (R. 169-170). Dill recorded the results of the May 12 tests as "etches perfect but no transconductance (10-50 microamperes per volt)" (PX 3, p. 215). He explained *1170 that when he first measured the devices, the transconductance was much smaller than he had anticipated, and he recorded "no transconductance." Upon more refined measurement, however, the device tested 10 to 50 microamperes per volt, which Dill testified was about one-tenth the transconductance of a conventional field effect transistor at the time (R. 91-92, 170-172). Dill admitted on cross-examination that at the time of making the tests, he felt that the measured values amounted to no transconductance for all practical purposes (R. 171). Immediately following the May 12 tests, Dill sought out the help of other colleagues in improving the performance of his device (R. 172-175). There followed a series of diligent attempts, extending over a period of several months, to construct a successful silicon-gate transistor. Rather than further developing the pyrolytic deposition process used in fabricating the May 12 device (R. 200), plaintiff's technicians experimented, unsuccessfully, with (1) use of a layer of silicon nitride in the device, (2) electron beam deposition of the silicon, and (3) silicon deposition by means of "sputtering" (R. 93-100, 183-184, 197-200). Thus, by the end of August, 1966, plaintiff had not constructed any better device than the May 12 transistor, and plaintiff had not attempted to improve the process used to prepare the May 12 device.

This Court concludes that plaintiff has not proven a reduction to practice on May 12, 1966. Assuming Dill's May 12 notebook entry accurately reports the test results, those results do not demonstrate the utility of the device for its intended use as a transistor. To prove a reduction to practice, a party must show that his experimental device performed the function for which it was designed. Schnick v. Fenn, 277 F.2d 935, 47 CCPA 1174 (1960), Voisinet v. Coglianese, 455 F.2d 1064 (Cust. & Pat. App.1972). A reduction to practice need not demonstrate that the invention operates as well as commercial devices, but this Court cannot find that the small transconductance reported would have persuaded practical men to take the risk at that time of commercializing the invention. Goodrich v. Harmsen, 442 F.2d 377, 58 CCPA 1144 (1971), Koval v. Bodenschatz, 463 F.2d 442 (Cust. & Pat.App.1972). This conclusion is supported by Dill's contemporaneous characterization of the results as "no transconductance" and by the simultaneous transfer of plaintiff's attention from the pyrolytic deposition process used in the May 12 device to other forms of fabrication. Plaintiff has failed to prove that more than a potential utility was established by the May tests of the silicongate device. See, Knapp v. Anderson, 477 F.2d 588 (Cust. & Pat.App.1973).

After the series of unsuccessful silicon-gate experiments, Dill returned to pyrolytic deposition under better conditions than previously employed, and new wafers for silicon-gate experiments were prepared in September, 1966 (R. 100-101). Dill testified that these new devices demonstrated transconductance "very similar" to conventional semiconductor transistors (R. 103), and his notebook entry for October 18, 1966, reports, "excellent curves, pure enhancement device" (PX 3, p. 249). Plaintiff, however, did not offer any corroboration other than the notebook entry for Dill's testimony as to the nature of the tests and their results. As this Court said in Waterman-Bic Corp. v. W. A. Sheaffer Pen Co., Division of Textron, Inc., 267 F. Supp. 849, 852 (D.Del.1967):

The date of invention cannot be predicated upon the unsubstantiated testimony of the patentee; there must be objective manifestations of the invention for the date to be carried behind the date of his constructive reduction to practice. These objective manifestations may take the form of disclosure to third parties, drawings or renderings.

Unlike the notebook entry of May 12, the October 18 entry provides no data elaborating on its characterization of the test results. The conclusory statement "excellent curves" provides no information *1171 to enable this Court independently to evaluate whether the tests demonstrated the utility of the device for its intended use. Consequently, these tests also cannot be considered a reduction to practice of the invention. Because of its conclusion that plaintiff's tests on the silicon-gate device in May and October, 1966, did not amount to an actual reduction to practice, and because the effectiveness of plaintiff's October 26, 1966, patent application as a constructive reduction to practice is not at issue in this proceeding, this Court finds that plaintiff first reduced its conception to practice with the October 26 patent application.

The defendant contends that the invention was made on behalf of General Micro-Electronics, Inc. (GMe), to whose rights the defendant has succeeded, by virtue of the activities of several GMe employees, and in particular Boyd G. Watkins and Richard Craig.

It contends that Boyd Watkins conceived the idea of the invention, that Richard Craig did the laboratory work necessary to reduce it to practice, and that the conception and reduction to practice occurred during late 1964 and early 1965. Relied upon to prove this is the testimony of Robert Norman, Donald Farina, Watkins, and Craig. Between January and July of 1965 Norman, a GMe vice president, was director of operations of the company "responsible for the gross profits of all operations of the company" (DX 20, p. 13). Apparently next in line was Donald E. Farina who in 1964-1965 was in charge of GMe's device and circuit research and development (DX 18, pp. 5-6). Boyd Watkins and Richard Craig were members of the engineering crew, Watkins reporting to Don Trotter (who did not testify in the case), Trotter in turn reporting to Farina (DX 17, pp. 12-13), and Craig reporting directly to Farina (DX 19, pp. 5-6). The testimony of these witnesses, a GMe proposal to the Air Force dated August 9, 1965 (DX 11) and a GMe interoffice memorandum from Watkins to Farina dated March 30, 1965 substantially constitute the basis for the defendant's contention that the silicongate field effect transistor through mesne assignments is defendant's invention.

The evidence points conclusively to the fact that the research and development group at GMe had in their minds the idea of using a silicon-gate process to make a self-aligning field-effect transistor, but there is no statement by any of the witnesses that Boyd Watkins was the one to conceive it. Neither Watkins himself nor Farina could say positively that Watkins was the one; in fact, Watkins could not pinpoint any particular time the idea occurred to him (DX 17, p. 37), and Farina would go no further than to say Watkins was "as close as anyone of the people in the group to the work being done in developing new structures and new device characteristics" (DX 18, pp. 48-49). Despite this, however, the Court concludes that the idea was conceived by one or more members of the GMe staff sometime prior to March 30, 1965,^[3] at which time Watkins wrote a memo (DX 12) to Farina in which he discussed the feasibility of evaluating the "polycrystalline silicongate process."^[4]

More difficult is the question of when the GMe staff's silicon-gate conception was reduced to practice. Early in 1965 *1172 Craig who was in charge of the research and development pilot line at GMe, the purpose of which was "to implement various kinds of devices, integrated circuits and experiments" (DX 19, p. 10), ran some experiments on silicon-gate transistors which continued for approximately 6 months or until July or August, 1965 (PX 19, p. 38). During this period of time Craig obtained all sorts of results. Some devices worked and some did not because of various problems (PX 19, p. 17). During this time Craig worked on many different devices of which the silicon gate was only one. His most specific answer as to results achieved in his experiments and tests with the silicon gate was:

There were devices that were open that didn't operate at all, for instance, due to various kinds of problems. There were devices that were shorted again due to various kinds of problems. Overdiffusion or who knows what all. Then other devices operated as normal transistors and had characteristics, thresholds and breakdown and so forth, that were considered normal (DX 19, p. 17).

Craig also testified in some detail about the process of making silicon gate devices and about the process of testing them.

The most that can be said for Craig's testimony, standing alone, is that he did a great deal of experimental work on the silicon-gate process prior to August, 1965, when the work "sort of petered out" (DX 19, p. 38). Craig's experimentation was marked by repeated process changes (DX 19, pp. 36-37), and he did not testify that any single device was both workable and reproducible, so as to amount to a reduction to practice. However, in support of its contention that Craig's tests amounted to a successful reduction to practice, defendant also relies on a GMe funding proposal to the Air Force (DX 11), the inter-office memorandum from Watkins to Farina dated March 30, 1965 (DX 12), and the oral testimony of Farina and Norman. No laboratory notebooks or records of actual test results were produced to substantiate the claim of a reduction to practice in 1965.

The GMe funding proposal for a Large Scale Integrated Circuit Array (DX 11) was drafted by Farina and submitted to the Air Force on August 9, 1965. The silicon gate technique was discussed at length in the Air Force Proposal (DX 11, pp. 2-1112-113). However, the drawings and description in the Proposal showed merely stylized devices and, as Watkins testified, did not accurately depict "either the conceptions that were discussed in the Lab or device work that had actually been done" (DX 17, pp. 80-81). This observation was confirmed by Farina who testified that the Air Force Proposal drawings were a description of "how one could fabricate a transistor, not how we had fabricated the transistor" and that at the time of the submission of the Proposal, GMe had no masks to make the device illustrated in the Air Force Proposal (DX 18, pp. 40-41). Watkins provided the following explanation for the lack of correlation between the devices described in the Proposal and the work actually done: ". . . I know the nature of our operation was you don't say any more than you had to say to anybody. Everybody was secretive in those days. Everybody thought they had a way to do it." (Emphasis added) (DX 17, p. 81).

One statement in the Air Force Proposal tends to indicate that a workable silicon-gate device had been prepared by GMe before August, 1965:

The silicon gate region can then be metallized in a normal manner to increase the gate contact conductivity. MOS threshold voltages of 6 volts have been achieved at GMe using this technique wherein the rest of the process has been relatively standard. (DX 11, p. 2-113).

Apparently, a six-volt threshold was in the range of commercially workable devices in 1965 (DX 18, p. 54). However, the value of this statement as evidence *1173 of a reduction to practice is undercut by the later statement in the Proposal that the "time required for proof of feasibility," meaning "establishment of a working process and the evaluation of a test vehicle" for polycrystalline silicon was nine months if funding were granted (DX 11, pp. 2-2172-218). This would indicate that the invention had not been reduced to practice as of the date of the Proposal. Nor does Craig's deposition corroborate the 6 volt figure contained in the Proposal. The lack of reference in Craig's testimony to obtaining a threshold voltage of 6 in any of his tests or experiments dilutes rather than strengthens the testimony of Farina in this respect. Viewing the document as a whole, this Court can only conclude that the Air Force Proposal is a document written to gain funding for further research rather than a precise disclosure of work accomplished. The Proposal does not support a conclusion that the silicon-gate conception had been reduced to practice before August, 1965.

The defendant also relies on DX 12, an inter-office memo from Watkins to Farina dated March 30, 1965.^[5] The memo stated seven advantages anticipated from the use of a recently developed test vehicle, none of which made any reference to the silicon-gate process. The only reference to the silicon-gate process in the memo argues the unfeasibility of preparing a test device "at present." Watkins explained that the "test vehicle" referred to in the memo of March 30, 1965 was not an actual functioning semiconductor device but rather a photographic mask which, with the aid of repeated applications of the photoresist process and other processing steps, could be made into an item of semiconductor hardware (DX 17, pp. 29-30). The March 30, 1965 memo and the testimony of Watkins relative to it convinces this Court that at some unspecified time prior to March 30, 1965, GMe had conceived of the invention, but there had been no reduction to practice.

If the documentary evidence does not substantiate defendant's contention of a reduction to practice in 1965, the oral testimony of defendant's witnesses provides only limited support.^[6] Watkins, the alleged inventor, could recall no specific event constituting a first reduction to practice of a silicon-gate transistor. He had only "sort of vague recollections of Dick Craig working on operation devices. That is to say, devices that were fabricated with the silicon-gate" (DX 17, pp. 39-40). Norman testified that he saw a semiconductor device having silicon-gate electrodes on it "probably in May or June, 65" (DX 20, p. 7), but there is nothing in his deposition that indicates he ever saw any test of any silicon-gate transistor that was a workable example; thus his testimony does not indicate that what he saw was any more than an experimental device, one of the many made by Craig on the pilot line. Only Farina testified to having witnessed successful tests of experimental silicon-gate devices.

Farina's testimony did not disclose any knowledge of the actual experimental work and while his testimony indicates he was familiar with the concept of the process he "did not personally perform the process and did not perform the masking steps and I just have to answer from my recollection of the process it was done like I just said" (DX 18, p. 53). Nevertheless, Farina testified that he witnessed tests on the devices and that some devices tested "reasonable thresholds or Vgst's" (DX 18, pp. 35-36). This testimony is entitled to limited weight in ascertaining whether a reduction to practice occurred because (1) it may refer only to occasionally successful results that were not reproducible, and *1174 (2) Farina claimed that Watkins was responsible for testing the devices as well as Craig, while Watkins disclaimed any participation in testing (DX 18, pp. 33-34; DX 17, pp. 39-40).

Viewed as a whole, defendant's documentary and oral evidence as to a reduction to practice in 1965 is inconclusive. Where there is reasonable doubt as to whether there has been an actual reduction to practice, it is appropriate for the Court to inquire into the inventor's subsequent conduct to determine if acts relied on as a reduction to practice amount only to an abandoned experiment. Fang v. Hankins, 399 F.2d 262, 55 CCPA 1468 (1968). Indeed, GMe's activities in connection with silicon-gate following August, 1965, provide persuasive evidence that no actual reduction to practice occurred in 1965.

After the work petered out about the time of the Air Force Proposal in August, 1965 nothing further was done on silicon-gate, Farina testified, because priority was given to conventional MOS structures and "probably, the biggest, most exact . . . [reason] . . . would be procrastination" (DX 18, p. 58). Watkins and another employee, Michael J. Selser, ultimately began to work on silicon-gate transistors sometime after they returned from a professional meeting at Evanston, Illinois, in the late summer of 1966, where they had heard a paper "that got them to thinking about the use of polycrystalline silicon as a gate electrode for MOS devices" (PX 19, p. 8). The idea was discussed with Farina and they were given the go ahead (PX 19, p. 8).

Selser testified that he came to work for GMe in November of 1965, that he was assigned to work in the field of polycrystalline silicon deposition on silicon wafers in late 1966 (PX 19, p. 8). He terminated his employment in June or July, 1968. He was never informed by anyone nor did he learn that any silicon-gate work was carried on at GMe prior to his work in the late summer of 1966. (PX 19, pp. 6, 17, 29) It is significant that during the time Watkins and Selser were working on the silicon-gate process, Craig was also working with Watkins and Selser (PX 19, p. 16). Selser saw Craig around the laboratory on a casual basis almost every working day (PX 19, p. 17), but during this period Craig never mentioned to Selser any previous work on the silicon-gate transistor (PX 19, pp. 16-17).

Selser's work was mostly concerned with achieving a successful deposition of polycrystalline silicon layers. This problem was never solved (PX 19, pp. 13, 17-18) and it was only at a late stage of his work that he succeeded in making a device that would function as a transistor (PX 19, pp. 17-18, 37-38).^[7]

During the course of Selser's work Dr. Clair Thornton who was director of research for the Philco-Ford Corporation, the then owner of GMe, learned of Selser's work and suggested that a patent application be prepared and filed on the process. This suggestion was made at a general meeting of the technical personnel attended by Craig, Watkins and Selser (DX 17, pp. 19, 20; DX 18, pp. 4, 17; PX 19, pp. 18-20, 39-40). Contact was made with Jack Wiseman, GMe's patent attorney. Wiseman commenced working promptly on the preparation of an application, consulting with Watkins and Selser. By the latter part of September, 1966 the application was completed. Both Watkins and Selser read and signed the application, and it was filed on September 26, 1966 (DX 16, pp. 20-22; PX 19, pp. 25-26; DX 1, p. 13).

The patent application filed on September 26, 1966, contained several defects in the disclosures. Philco-Ford's Dr. Thornton noted that fact, the corrections were made, and on November 17, 1966, a substitute application was filed (DX 2; DX 16, pp. 33-35; DX 18, pp. 16-17; PX 19, pp. 23-24). It is inconceivable *1175 that if, when Selser began his work, there had been at GMe a prior reduction to practice or for that matter any concerted effort to reduce the silicon-gate idea to practice, Farina, Watkins, Craig or Wiseman, (who the defendants contended also knew of the tests in 1965), would not have mentioned it to Selser or discussed some phase of it in his presence while preparing to file the application for the patent. Therefore, this Court must conclude, after assessing all of the credible evidence, that no actual reduction to practice of the silicon-gate invention occurred at GMe before the work "petered out" around August, 1965.

Defendant contends that even if it is not entitled to a reduction to practice date in 1965, its patent application of September 26, 1966 (DX 1) operates as a constructive reduction to practice. Plaintiff claims that the specification of that application discloses an inoperative device and therefore cannot be considered a reduction to practice.^[8]

The statutory test for the sufficiency of a patent specification is that it "shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same. . . ." 35 U.S.C. § 112. To prove that the September 26, 1966 application was legally inadequate, plaintiff is required to show (1) that it described an inoperative device, and (2) that the device so described could not be made operative by changes obvious to one of ordinary skill in the art. Nicolaou v. Cooperman, 438 F.2d 993, 58 C CPA 938 (1971); Field v. Knowles, 183 F.2d 593, 37 CCPA 1211 (1950); Carlson Hoist & Machine Co. v. Builders Equipment Corp., 96 F.2d 145 (2nd Cir. 1938); Balaban v. Polyfoto Corporation, 47 F. Supp. 472 (D.Del.1942).

Defendant admits that this application teaches, both in its drawings and text, an inoperative device (Pretrial Order, pp. 8, 19; Def.Br. p. 48). Its defect is that the source and drain regions of the device are described as connected, causing in effect, a short circuit. Since there is no question of the defectiveness of the device disclosed, the sufficiency of the September, 1966 application as a reduction to practice hinges on whether the recognition of and cure for this short-circuit was obvious to one of ordinary skill in the art.

On the question of what constitutes ordinary skill in the art of semiconductor processing, the relevant art for this invention, plaintiff's expert, Dietrich Jenny, and defendant's expert, Robert Musa, were in virtual agreement. Jenny testified that there are three levels of specialists involved in processing semiconductors: the engineer who designs a device; the mask maker who prepares the photoresist mask; and the processor who constructs the device according to established instructions (R. 390). Musa testified, "from 1963 on, the typical mask operation consisted of specialists who could take engineering information and given the design rules that I spoke about, compile these into working masks. Now, very often the design engineers worked with the specialists and very often he did not he gave them schematic diagrams and they could reduce them to masks." Musa elaborated that these semiconductor "specialists" were draftsmen, persons trained in mechanical drawing, who could be trained to follow design rules and to draw up photoresist masks (R. 622). Taking the testimony of these two experts together, this Court finds that a person of ordinary skill in the semiconductor processing art in 1966 was a draftsman with sufficient training to engage in mask preparation and *1176 semiconductor construction following established instructions.

The evidence further establishes that a person of ordinary skill in the art would not know how to cure the short-circuit taught by the September, 1966 patent application. There was some dispute among the witnesses over the efficacy of proposed remedies for the short-circuit (compare, e. g. R. 381-384 with R. 626-631), but there was no persuasive testimony by any witness that a suitable cure was obvious to one of ordinary skill in the art as here defined. Jenny testified that a person of ordinary skill could not repair the shortcoming of the application and come up with a workable device (R. 384). He further asserted that even a processor with greater than ordinary skill might have had difficulty designing masks in which the source and drain did not run together, otherwise following the teaching of the September application (R. 405). Dill's testimony agreed with these statements (R. 136-137).

Defendant's witnesses testified that recognition and cure of the application's defect was obvious to a semi-conductor designer, but plainly, a designer's skills were greater than those of a draftsman. Watkins, the purported inventor, testified, "I'm fairly good at topological recognition and it [the application's defect] would be fairly obvious to me." (DX 17, pp. 69-70).^[9] Farina stated, "It is my opinion that if one were to attempt to make a device from these drawings and from the patent application, that it would become obvious to the semiconductor designer that the photo-resist mask must protect the ends of the silicon gate." [Emphasis added] (DX 18, p. 31). The following testimony on direct examination of Musa was more thorough than that of Watkins or Farina:

Q. As of September, 1966, if someone skilled in the semiconductor processing art saw in an actual experimental device an error corresponding to that in the application we have been discussing where the source and drain areas ran together instead of being separated, and if such a person wanted to fix that error, in your judgment to what degree would such a person, one normally skilled in the semiconductor processing art, have been capable of doing so?

A. That is a difficult question to answer. For normal devices almost anybody associated with MOS manufacture could make the correction. For silicon gate devices, because of the novelty of the processing or because of the unusualness, you would very rapidly limit the number of people who could make such a decision, and it probably would be not more than certainly all engineers could, most senior type designers could, but I don't think the standard draftsmen or something like that could.

Q. Of the people who in your judgment could have corrected that error as of 1966, to what extent would they have been, in correcting that error, exercising inventive ingenuity, to what extent would they have been exercising the normal skill of the art, and to what extend would they have been exercising the elementary skills of the art?

A. Well, in a case like this, I don't think that the person making up the actual art work, the person making up let's say the drawings, would make the correction himself. He would go back to whoever was the original designer and want to know, `What goes with this? It doesn't make sense.'

Q. I am talking about the original designer.

A. Well, the original designer, it would be perfectly obvious to him it *1177 can't work. . . . He does not have to invent. The means already exist. What he must do is exercise normal expected skill of a design engineer. [Emphasis added] (R. 640-641).

In light of all the testimony, this Court can only conclude that a draftsman of ordinary skill in 1966 might have perceived the defect in the September application but would not have had sufficient skill to make the necessary modifications to construct an operable device. Therefore, the September, 1966, application failed to describe adequately the manner and process of making the silicon-gate device, and this application was not a constructive reduction to practice.

In summary, this Court has found: (1) that the GMe organization conceived of the silicon-gate invention by March, 1965; (2) that GMe did not reduce the invention to practice in 1965; (3) that Hans Dill independently conceived of the silicon-gate invention on May 1, 1966; (4) that GMe's patent application of September 26, 1966 did not constitute a constructive reduction to practice; (5) that Dill did not reduce his invention to practice until the filing of his patent application on October 26, 1966; (6) that GMe did not reduce its invention to practice until the filing of its patent application on November 17, 1966. Thus Watkins, although arguably first to conceive, was last to reduce to practice.

The relevant statute, 35 U.S.C. § 102(g) plainly provides that where the first party to conceive is last to reduce to practice, he is entitled to priority only upon a showing of reasonable diligence from the time just prior to conception by the other inventor. Accordingly, defendant must demonstrate GMe's diligence from April, 1966 until reduction to practice in November, 1966.

The record before this Court demonstrates that GMe was not diligent in reducing its conception to practice throughout the relevant period. Craig, who was responsible for testing GMe's silicon-gate devices in 1965, testified that the project "sort of petered out" around August of 1965 (DX 19, p. 38). Farina explained the year delay between the opening of a docket containing the portion of the Air Force Proposal on the silicon-gate concept in the records of GMe's patent attorney in September, 1965 and the first patent application in September, 1966, principally in terms of "procrastination" (DX 18, p. 58).^[10] Defendant has offered no evidence of any further attempt at reducing the invention to practice after its silicon-gate work was discontinued in the fall of 1965, until Selser began working on a new silicon-gate project with Watkins in the "late summer" of 1966 (PX 19, p. 10).^[11] Thus it is undisputed that there was no significant effort at reducing the silicon-gate concept to practice for a period of four or five months after April, 1966, when defendant was chargeable with diligence. The party chargeable with diligence under 35 U.S.C. § 102(g) must account for the entire period during which diligence is required, Gould v. Schawlow, 363 F.2d 908, 53 CCPA 1403 (1966). Because defendant cannot prove any diligence for a substantial period, it has failed to make the necessary *1178 showing of reasonable diligence, and the plaintiff must be awarded priority.

The foregoing opinion is adopted as the Court's findings of fact and conclusions of law in accordance with F.R.Civ. P. 52(a), 28 U.S.C.

This Court awarded the plaintiff in this patent infringement action priority of invention, 35 U.S.C. § 102(g), in an opinion dated February 22, 1974. Defendant has requested permission, pursuant to 28 U.S.C. § 1292(b), to appeal this interlocutory decision. Defendant contends that this Court erred in two respects and that each error, as § 1292(b) requires, "involves a controlling question of law as to which there is substantial ground for difference of opinion and that an immediate appeal from the order may materially advance the ultimate termination of the litigation." Having considered the briefs and oral argument of the parties, this Court must deny defendant's request.

The first issue on which defendant claims this Court is in error is the evaluation of the level of skill in the art of semiconductor processing used in determining the adequacy under 35 U.S.C. § 112 of defendant's patent application of September 26, 1966. While this Court does not deny that there may be legitimate difference of opinion as to the ordinary skill in the art at the relevant time, the determination of that level is a factual determination. In reaching its conclusion on the ordinary level of skill in the art, this Court carefully considered the testimony of the expert witnesses on this issue. In this connection, the Court found most instructive the implication by defendant's expert Robert Musa that trained draftsmen were skilled in the semiconductor processing art (R. 640-641).

Defendant urges that the ultimate question of patent validity, which depends on a finding as to the skill in the relevant art, is considered a question of law, and a district court's disposition thereof may be reversed on appeal even though not clearly erroneous. Hadco Products, Inc. v. Walter Kidde & Company, 462 F.2d 1265, 1268 (3rd Cir. 1972). However, the ordinary level of skill in the art is only one ingredient of the ultimate question of validity.^[1] Like the reasonable man standard of civil jurisprudence, it is subject to some flexibility depending on the circumstances of the particular case. The question of who is a person ordinarily-skilled in the art can, with sufficient ingenuity, be characterized either as law or fact; but in the final analysis, resolving it requires more estimation as to a state of events selection of the person of meaningful, representative skill in the relevant art than application of established criteria to a state of events. Typically, determination of the ordinary skill in the art is not the end of the road, for the Court must subsequently measure the patent disclosure against that level of skill. In the instant case, even if the Court had adopted defendant's position that a designer, instead of a trained draftsman, was of ordinary skill in the art, the Court still would have had to resolve a dispute between the experts as to whether even a person so skilled could have corrected the defective patent disclosure without invention. For all of these reasons, this Court cannot conclude that the level of skill in the relevant art is a "controlling question of law" so as to warrant interlocutory review under § 1292(b). The pertinent authorities, while not dispositive of this issue, are consistent with this Court's position. See, e. g., Hogg v. Emerson, 11 How. 587, 52 U.S. 587, 606, 13 L. Ed. 824 (1850); Locklin v. Switzer Bros., Inc., 299 F.2d 160, 166 (9th Cir. 1961), cert. denied, 369 U.S. 861, 82 S. Ct. 950, 8 L. Ed. 2d 18, reh. denied, 369 *1179 U.S. 891, 82 S. Ct. 1157, 8 L. Ed. 2d 291 (1962); Carter-Wallace, Inc. v. Otte, 474 F.2d 529, 547 (2nd Cir. 1972).

Furthermore, this Court is not persuaded that adoption by the Court of Appeals of a higher level of skill in the art as the standard for this case would materially advance the ultimate termination of this litigation. Were the Court of Appeals to find, using the higher standard, that defendant's patent application of September 26, 1966 was adequate, plaintiff would then seek review of this Court's determination, inter alia, that plaintiff's assignor failed to reduce his conception to practice in May of 1966, well before defendant's September application. In other words, even if defendant were successful on the first issue, complex issues would remain on appellate review.

The second issue raised by defendant's request for permission to appeal, but not pressed by defendant at oral argument, is whether this Court erred in finding that the GMe silicongate conception was not reduced to practice in 1965. There is little doubt that if this contention were successful, defendant would be awarded priority and the litigation would be at an end. Nevertheless, this Court finds that its evaluation of GMe's experimental activities in 1965 did not turn on a controlling question of law. In determining that no reduction to practice occurred in 1965, this Court weighed the two documents bearing on the issue, carefully scrutinized^[2] the oral testimony of defendant's witnesses, and measured that testimony against the revealing subsequent conduct of those witnesses. These determinations are not suitable for interlocutory appellate review as a controlling question of law. Defendant quarrels with "stress" placed by the Court on certain of the facts, but defendant has failed to demonstrate, by citation of authorities or by argument, that a controlling question of law is at stake.

[1] 35 U.S.C. § 102(g).

[2] Since the only issue before the Court is priority, the Court does not have before it the issue of the validity of the patent issued to the plaintiff.

[3] DX 12; DX 17, pp. 28, 34-40, 86-87; DX 18, pp. 33-34; DX 19, p. 14; DX 20, pp. 4-5. The Court does not here decide whether Boyd Watkins was the sole inventor.

[4] The memo stated in relevant part: "The test vehicle can be used for evaluating the polycrystalline silicon-gate process but optional masks will have to be designed and cut. Considering the present state of our polycrystalline film development and the over-loaded conditions in our own mask making area, it was not considered feasible to design and cut these optional masks at present."

[5] Quoted at note 4, supra.

[6] Oral testimony offered to prove a reduction to practice prior to the date of a patent application demands careful scrutiny. The Barbed Wire Patent, 143 U.S. 275, 284-285, 12 S. Ct. 443, 36 L. Ed. 154 (1892); Jones Knitting Corporation v. Morgan, 361 F.2d 451, 455-456 (3rd Cir. 1966); S. W. Farber, Inc. v. Texas Instruments, 211 F. Supp. 686, 692 (D.Del.1962).

[7] Defendant does not contend that Selser's functioning device constituted a reduction to practice before plaintiff's patent application.

[8] Plaintiff does not here contest that defendant's application of November 17, 1966 (filed some three weeks after Dill's patent application) constitutes a constructive reduction to practice.

[9] Watkins also testified that "anyone anywhere in any way skilled in the art" would have known that the source and drain regions had to be separated and "people skilled in the art" would have been able to separate the regions successfully "with no effort, no trouble" (DX 17, pp. 71-72). The Court places greater weight on the detailed testimony of Musa than on these assertions by Watkins.

[10] Wiseman, GMe's patent counsel, maintained an open file labeled "Semiconductor Resist. MOS Invention" containing silicongate material, beginning in September, 1965. However, no dated entries were made in that file (DX 10A) in 1966 until September. Plainly, this open file without entries during much of the relevant period does not constitute evidence of diligence.

[11] Plaintiff asserts that the cessation of GMe's silicon-gate activities for the year following August, 1965 constitutes "abandonment" under 35 U.S.C. § 102(g). However, plaintiff has not demonstrated by "clear and convincing evidence", Struthers Scientific and International Corp. v. General Foods Corp., 314 F. Supp. 313 (D.Del.1970), that GMe deliberately discarded silicon-gate rather than merely placed priority on other projects.

[1] This Court agrees with defendant that the definition of the person skilled in the art is the same whether the issue is patentability, 35 U.S.C. § 103, or as here, adequacy of the specification, 35 U.S.C. § 112.

[2] See footnote 6, Opinion of February 22, 1974.