Rambus Inc. v. Rea, No. 12-1634 (Fed. Cir. 2013)
Annotate this CaseConventional memory circuits asynchronously transfer all of the data upon request, which can tie up the computer system for long periods of time and create a “bottleneck” that slows down computer operations. The patent at issue solves the problem using a synchronous memory system to transfer data. The Board of Patent Appeals and Interferences held that certain claims of the patent were invalid for anticipation and obviousness. The Federal Circuit held that the Board correctly construed claims: that the “external clock signal” only requires the clock to be periodic during the data input phases, as opposed to being periodic for all system operations and that “write request” could include “the state of a signal,” which is usually represented by a single bit. The court vacated with respect to the obviousness determination.
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