Application of Hugo Ghiron and Werner Ulrich, 442 F.2d 985 (C.C.P.A. 1971)

Annotate this Case
U.S. Court of Customs and Patent Appeals (1909-1982) - 442 F.2d 985 (C.C.P.A. 1971) May 20, 1971

Robert O. Nimtz, attorney of record, Murray Hill, N. J., for appellant.

S. Wm. Cochran, Washington, D. C., for the Commissioner of Patents; Jere W. Sears, Washington, D. C., of counsel.

Before RICH, ALMOND, BALDWIN, LANE, Judges, and FORD, Judge, United States Customs Court, sitting by designation.


This appeal is from the decision of the Patent Office Board of Appeals sustaining the examiner's rejection of claims 6-12 of appellants' application1  and further refusing allowance of those claims on two new grounds under Rule 196(b) of the Patent Office Rules of Practice. Five claims have been held to be "in condition for allowance."


The invention relates to a method of facilitating transfers dictated by programs for processing data in a computer operating in overlap mode.

As pointed out by the application, a program is a set of instructions for carrying out prearranged operations on data by use of processing equipment. In stored program digital computer operations, the instructions are placed beforehand in a memory known as a program store, with each instruction having an address giving its location in the store. Typically the addresses are assigned sequentially to the instructions making up the steps of a program. The stored instructions may contain a command portion specifying an operation to be performed and an address portion giving the address in storage of data to be employed in performing that operation. Thus a step of a program may contain portions that cannot be acted upon simultaneously. As an example, the command portion of an instruction to read data out of a data store necessarily cannot be executed until the instruction itself has first been obtained and its address portion has subsequently acted on the data store to determine the storage position from which data will be "read" in accordance with the command portion.

The non-interfering portions of sequential program steps may be made to overlap to speed up operation. Using three sequential instructions as examples, the addressing of the program store for the third (in time sequence) instruction can take place at the same time that the data store is being addressed in accordance with the address portion of the second instruction and the command portion of the first instruction of the sequence is being executed.

In any one subroutine or subset of operations, the addresses of the instructions in the program store are ordinarily assigned sequentially with the address register being incremented by one after each addressing operation is made. However, it is frequently desired to interpose another subroutine, the instructions for which are located at a different sequence of addresses in the program store. For such a case, a transfer instruction must be interposed in the program. The transfer instruction contains the location in the program store of the first instruction of the new subroutine. When a transfer instruction is interposed in overlap mode operations as discussed above, additional instructions from the first subroutine continue to be addressed in the program store between the time of addressing the transfer instruction and its execution. These additional instructions are not wanted and must therefore be blocked out. Blocking them out requires particular equipment in the computer. Also, machine time is wasted in partially processing these unwanted instructions.

Appellants' invention avoids these undesirable aspects of a transfer during overlap mode operation by introducing the transfer instruction into the program several steps before the final instruction or the instruction after which interposition is to take place. The point of introduction is selected so that the transfer instruction identifying the position in the program store to be addressed for the first step or instruction of the new subroutine reaches the execution stage in the computer at a time such that this position is addressed immediately after the last desired instruction of the original routine is so addressed. The first instruction of the new subroutine will then be effective to address the data store during the same machine cycle in which the command portion of the last wanted instruction of the original routine is being executed and will have its own command portion executed during the following machine cycle. Thus, no unwanted instructions from the first routine are addressed in the program store, and no blocking out of partially processed instructions is necessary.

The appealed claims, to appellants' method,2  have been treated by the board in two groups, of which claims 6 and 11 are representative:

6. In programmed data processing, the method of facilitating a transfer from one subset of program instructions to another, which comprises the steps of

(1) storing signals representing the instructions of the subsets,

(2) storing signals, representing an instruction dictating a transfer from one subset to another,

(3) commencing to extract from storage, and commencing to execute, said signals representing the instructions of the one subset,

(4) extracting from storage, and executing, said signals representing the transfer instruction before executing the signals representing the last instruction of said one subset, and

(5) executing the signals representing the last instruction of said one subset immediately followed by executing the signals of said other subset to which a transfer is made in accordance with said transfer instruction.

11. In programmed data processing, the method of facilitating a transfer from one set of program instructions to another, which comprises the steps of

(1) storing the instructions of the one set in sequential locations of a store, and including an instruction for transferring from said one set to the other set at an intermediate location of said sequential locations,

(2) storing the instructions of said other set in sequential locations, different from the first, of said store,

(3) initiating the extraction of the instructions of said one set in sequence, and

(4) processing the instructions thus extracted on an overlap basis for which one instruction is being at least partially executed at the same time the succeeding instruction is being extracted from said store, whereby an instruction of the one subset, to which a transfer is made in accordance with the transfer instruction, is extracted from said store at the same time the last instruction of the other subset is being executed.


The sole rejection by the examiner was on the ground that the method claimed amounts to the inherent function of the apparatus. This rejection and the board's decision sustaining it, were made prior to our decision in In re Tarczy-Hornoch, 397 F.2d 856, 55 CCPA 1441 (1968). That decision, as recognized by the solicitor, overruled the line of previous decisions sanctioning that theory of rejection. Hence, the board's decision, insofar as it relied on that ground of rejection, must be reversed and requires no further discussion.

One of the new grounds of rejection which the board advanced is a prior art rejection stated to be "under 35 U.S.C. 102 and 103." The sole reference is a description in the Proceedings of the Institute of Radio Engineers (I.R.E.)3  of the construction and operation of a computer designated SEAC (Standard Eastern Automatic Computer) made at the National Bureau of Standards in 1950. The other new rejection was on the ground that appellants' disclosure is insufficient to satisfy the requirements of 35 U.S.C. § 112, first paragraph. Instead of electing to have these new rejections considered by the primary examiner as permitted under Rule 196(b), appellants followed an alternative procedure in petitioning for reconsideration by the board. The petition was considered but denied insofar as it requested modification of the original decision.


The I.R.E. publication describes SEAC as an automatic high-speed computer which operated at a "1 mc" pulse repetition rate, was "predominantly serial in nature," and used binary number representation. The computer is described as performing 16 types of operations (addition, subtraction, read in, print out, etc.). The instruction words are said to have expressed those operations in either a four-address or a three-address mode. The four address instruction word is represented in Figure 2 as follows:


In describing the operation of SEAC, the publication states:

The component parts of an instruction word in both the four-address and three-address systems are shown in Fig. 2. In the four-address system the addresses are denoted by the symbols α, β, γ, and δ. Normally α is the address of the first operand, β the address of the second operand, γ the address of the result of the operation, and δ the address of the next instruction. The instruction also contains a code specifying the type of operation to be performed and a conditional halt-control digit in the sign position. An address comprises ten binary digits, so it can designate one out of 210 or 1,024 memory cells. This is sufficient for the two SEAC memories. Four binary digits specify the operation to be performed. The sixteen different operation codes thus available are now all used. The single binary digit in the sign position indicates whether or not the computer is to halt after performing the operation. In the course of executing one instruction, the control of the computer cycles through four phases, one for each reference to the memory. In a typical address β is referred to in phase 2, α in phase 3, γ in phase 4, and δ in phase 1.

The board first held claims 6 and 8 to be "fully anticipated" by the operation of the SEAC computer as described in the reference. In applying the reference, the board relied on the four-address mode of operation of SEAC. It observed that " [e]ach program instruction" in such operation included the α, β and γ address of the location of the two data operands and the address of the result, and the δ address of the "location in the memory of the next instruction." In reaching its conclusion regarding claims 6 and 8, it reasoned:

The delta address is processed in the machine before any of the other three addresses of an instruction word in the first of the four phases of a computer cycle. (Page 1301, top of column 2.)

The normal sequence of a series of instructions that constitute a subset or subroutine is in successively numbered memory positions and each instruction of such a subset, except the last, would have the appropriate delta address to process consecutive memory locations for the next instruction. However, the last instruction of a subset would have a delta address directing a transfer to a nonsequential memory location for the first instruction of a second subset.

Since the delta address always is extracted from storage and processed in phase 1 of a four phase machine cycle, this address is a "signal representing the transfer instruction" which is executed before the other three addresses and the operation code which represent the last instruction of the first subset. Thus SEAC was instructed as to a fourth coming transfer to a subsequent subset before the last instruction of a prior subset without loss of processing time and without requiring additional apparatus to block the processing of the next successive memory location.

Claims 6 and 8 we consider to be fully anticipated in the operation of the SEAC computer in an obvious manner from the above.

The basic premise for this reasoning lies in the statement that the delta address is "processed before any of the other three addresses of an instruction word". The "Page 1301, top of column 2", relied on to support that premise, refers to the last sentence of the paragraph of the I.R.E. publication quoted above. That sentence, which bears repeating, reads

In a typical address β is referred to in phas 2, α in phase 3, β in phase 4 and δ in phase 1.

The board thus interpreted the designation of the referral to the δ address as "phase 1" in the sentence to mean that the δ address is accessed prior to the other three addresses of the same four-address instruction word. In our opinion consideration of the full description of the operation of SEAC in the reference compels the conclusion that it did not operate in such a manner.

Even taking the sentence out of context, as the board obviously did, there is an equally reasonable alternative interpretation. Thus the reference to referral to the addresses in the sequence β (phase 2), α (phase 3), γ (phase 4) and, lastly δ (phase 1), is indicative of an actual time sequence of the referrals in the order they are listed — with the δ address accessed last. Looking past the bare sentence, the fact that the δ address is described as the address of "the next instruction" (obviously meaning the next four-address instruction word) leads to the logical conclusion that it is the sequence in which the addresses are listed in the sentence, rather than the phase designation, which reveals the actual time sequence. It is apparent that, as stated by appellants, SEAC was a "simple serial mode computer", and no purpose would be served by accessing the next instruction word before the operations required by the current instruction word were executed.

Further light is shed on the present question by the description of a comparison operation by SEAC, set out in the reference as follows:

The main difference between the three- and four-address systems is in the designation of the next instruction to be performed. In the four-address system the instruction contains an explicit statement (δ) designating where the next instruction is located in the memory. In the three-address system, however, there is no such explicit statement. Instead, instructions in this system are automatically sequenced in accordance with a convention, successive instructions being normally located in consecutively-numbered memory positions. An exception to this convention is available through the comparison (conditional transfer) operation, whenever the first operand (α) is less than the second operand (β). In this case the result of the comparison leads to what is called a "jump" operation in which the next instruction for both the three-address and four-address systems is chosen from address γ.

This operation requires that the first operand (α) and the second operand (β) be compared to determine whether there is to be a "jump" to the γ address for the next instruction word instead of it being taken from the δ address. It plainly precludes accessing the δ address before the α and β addresses of the same instruction word.

In response to the position taken by the board, appellants submitted an affidavit of an engineer employed by the National Bureau of Standards who participated in the design, construction, and operation of SEAC. The affiant asserts that SEAC actually utilized the δ address only after the α, β, and γ addresses of the same instruction were utilized. He states that SEAC had no provision for utilizing a δ address from an instruction first. As pointed out by the board on reconsideration, however, the affiant does not discuss the I.R.E. description of SEAC, which is the reference rather than SEAC itself. The affidavit has little value, therefore, apposite to the pertinent issue of interpretation of the reference. Nevertheless, it is indicative of how SEAC actually worked and of the knowledge of the art with regard to that computer.

For the reasons already discussed, we have concluded that a person of ordinary skill in the art would not find the reference to disclose a computer which would be operable to access an instruction to transfer to another subset or subroutine of instructions before completion of the other instructions of the current subset. It follows that the rejection of claims 6 and 8 under 35 U.S.C. § 102 as anticipated by the I.R.E. was in error and must be reversed.

Claims 7, 9, 10, 11 and 12 differ from claims 6 and 8 in that they require control of the instructions on an overlap basis. The board held these claims to be anticipated (§ 102) by the reference on the ground that early processing of the δ "instruction", as it found the reference to have taught that SEAC could do, amounted to operation on an "overlap basis" as to portions of the instruction. It alternatively held that it would be obvious (§ 103) to process the four-address instruction word of SEAC in overlap mode, that mode of processing admittedly being old.4  Both of these rejections, however, are predicated on the interpretation of the reference as describing SEAC as accessing the δ address before the other addresses in the same instruction word. Therefore both these grounds of rejection must fall with that interpretation as does the rejection of claims 6 and 8. Accordingly, the decision of the board is reversed as to the prior art rejections of claims 7, 9, 10, 11 and 12.

The board based this rejection on the alleged failure of appellants' disclosure to meet the requirements of the enablement provisions of the first paragraph of § 112. Its position was that definite apparatus is required to practice the claimed method; that an adequate disclosure of how to practice the method requires a disclosure, or reference to a disclosure, of suitable apparatus; and that the present application lacks such a disclosure.

At the outset, one point needs particular discussion. In their arguments appellants seem to imply that, because the claims on appeal are method claims, it is not material whether there is an adequate disclosure of the apparatus. This is clearly not so. Appellants do not deny that the application must be adequate to teach how to practice the claimed method. If such practice requires particular apparatus, and we think it plainly does, it is axiomatic that the application must therefore provide a sufficient disclosure of that apparatus if such is not already available.

The focal point of the board's rejection on this ground was the application drawings, submitted as being illustrative of a data processing system embodying appellants' improvement. These drawings are in the form of what have been characterized as "block diagrams", i. e., a group of rectangles representing the elements of the system, functionally labelled and interconnected by lines. As pointed out by the board, the specification does not particularly identify each of the elements represented by the blocks or the relationships therebetween, nor does it specify particular apparatus intended to carry out each function. This disclosure, stated the board, amounts to "no more than a direction to select apparatus from the prior art that will produce the results required to practice the process."

The rejection could not be sustained if this were the sole reasoning of the board with regard thereto. As urged by appellants, if such a selection would be "well within the skill of persons of ordinary skill in the art", such functional-type block diagrams may be acceptable and, in fact, preferable if they serve in conjunction with the rest of the specification to enable a person skilled in the art to make such a selection and practice the claimed invention with only a reasonable degree of routine experimentation. The board's later comments, however, make it clear that it was questioning not only appellant's assertion that the selection and assembly of the components required to practice the claimed process were within the skill of persons in the art but also the fact that such selection and assembly could be carried out routinely.5 

As the board plainly found, and is apparent from the application, the method in issue cannot be performed by a general purpose computer of the prior art. Appellants concede as much in stating that their invention "is a modification to prior art overlap computers" (emphasis ours). Specifically, it appears that the computer appellants use must be capable of accepting early transfer instructions without causing blocking out of the instruction or instructions immediately following. Appellants state that transfer instructions in conventional overlap operation do cause such blocking out. It also appears correct, as stated by the board on reconsideration, that

many of the components which appellants illustrate as rectangles in their drawing necessarily are themselves complex assemblages that can have widely differing characteristics that must be precisely coordinated with other complex assemblages. It is common knowledge that many months or years elapse from the announcement of a new computer by a manufacturer before the first prototype is available. This does not bespeak of a routine operation but of extensive experimentation and development work that would be inconsistent with appellants' bare allegation that the instant disclosure would put a person of ordinary skill in the art in possession of the apparatus to carry out the claimed method. The lines interconnecting the rectangles of appellants' drawings do not represent electrical conductors but merely indicate the routing of intangible data or information between functional modules.

So far as we are able to determine from this record, the board had a reasonable basis for questioning the adequacy of the instant disclosure. It thus became incumbent on appellant to rebut this challenge. See In re Cook, Cust. & Pat. App., 439 F.2d 730, decided April 8, 1971 and In re Marzocchi, Cust. & Pat. App., 439 F.2d 220, decided April 15, 1971.

To rebut the board's position, appellants referred to a textbook asserted to show computer components and circuits6  and to certain classes in the Patent Office classification system (apparently relating to computer circuits). They urge that this evidence makes it clear that the selection and assembly of the components they require is "well within the skill of persons of ordinary skill in the art." The evidence is meager and the argument merely conclusionary. Not being experts in computer or electronic technology, we cannot conclude from such a showing that the board erred. More particularly, the showing is not persuasive that a person of ordinary skill in the art would be able to provide apparatus for practicing the present invention from appellants' drawing taken in connection with their specification. Neither does it demonstrate that such a person would be taught how to modify previously known "overlap mode" computers to practice the invention.

It is further urged by appellants that the examiner found the disclosure adequate because he allowed apparatus claims in the application. That argument has been considered. However, the examiner did not make an express holding on the question of adequacy of disclosure. We cannot speculate on what his view would have been if the present question had been raised specifically before him. The position taken by the board is the one we must consider. Since appellants have not convinced us by evidence or argument that that position is erroneous, the board's action must be sustained.

The decision of the Board of Appeals is affirmed.



Serial No. 543,756, filed April 19, 1966, for "Programmed Data Processing With Facilitated Transfers," designated a continuation of Serial No. 244,396, filed December 13, 1962


Claims drawn to apparatus have been held to be in condition for allowance


Volume 41, No. 10, October 1953, pages 1300-1313


We observe that the record contains no assertion by the Patent Office that it would be obvious, independently of the teaching erroneously found by the board in the cited reference, to program a known computer which operates in an overlap mode so as to access a transfer instruction prior to the completion of the other instructions in the same subset as set out in the claimed technique


We are in complete agreement with the following statement of the board on this latter point:

It is well settled that a routineer in an art has an expertise above that of the unskilled person, but if the selection of suitable apparatus requires unreasonable experimentation and delays for him to come into possession of the apparatus that could carry out the invention, a disclosure thus deficient would not be adequate legal consideration for the grant of a patent.


"Digital Computer Components and Circuits", by R. K. Roberts, Von Norstrand, 1957