Mentor Graphics Corporation v. EVE-USA, Inc. et al, No. 3:2010cv00954 - Document 483 (D. Or. 2014)
Court Description: OPINION AND ORDER. See order for full text regarding constructions. Signed on 3/6/14 by Judge Michael W. Mosman.Associated Cases: 3:10-cv-00954-MO, 3:12-cv-01500-MO, 3:13-cv-00579-MO (dls)
Download PDF
<![CDATA[
UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION MENTOR GRAPHICS CORPORATION, an Oregon Corporation, Plaintiff/Counter-defendant, Case No. 3:10-cv-954-MO (lead) Case No. 3:12-cv-1500-MO Case No. 3:13-cv-579-MO v. OPINION AND ORDER EVE-USA, INC., a Delaware corporation; and SYNOPSYS EMULATION AND VERIFICATION S.A., formed under the laws of France, Defendants/Counter-claimants. SYNOPSYS, INC., a Delaware corporation; EVE-USA, INC., a Delaware corporation; and SYNOPSYS EMULATION AND VERIFICATION S.A., formed under the laws of France, Plaintiffs/Counter-defendants v. MENTOR GRAPHICS CORPORATION, an Oregon corporation, Defendant/Counter-claimant. 1 OPINION AND ORDER MOSMAN, J., On February 24, 2014, I held a claim construction hearing in the above-entitled patent actions. At issue were claim terms appearing in U.S. Patent Nos. 7,069,526 ( 526 patent ), 6,240,376 ( 376 patent ), 5,649,176 ( 176 patent ), 6,009,531 ( 531 patent), and 6,947,882 ( 882 patent ). In this Order, I announce my constructions of the following terms: Claim Term Construction 526 Patent design visibility design patching design control instrumentation circuitry aspect integrated circuit product monitoring the entire or partial state of the DUT at, and relative to, predetermined events altering the behavior of the DUT to a predetermined particular desired state at predetermined events methods to specify the events that control design visibility and design patching additional circuitry to facilitate debugging portion one or more manufactured or configured chips that implement a design in the target technology 376 Patent gate-level netlist gate-level design a list of gates and their inputs, outputs, and interconnects a list of gates and their inputs, outputs, and interconnects instrumentation signal simulating a gate-level design sensitivity list process generating logic output signal added or preserved during logic synthesis that indicates whether a corresponding RTL source code statement is active modeling the operation of a gate level design using software and/or hardware a list of signals to which a process is responsive a description of the behavior of some portion of a circuit design generating gates 176 and 531 Patents logic system configurable logic system environment a system including one or more configurable logic devices into which the circuit design under test is configured a system including one or more configurable logic devices into which the circuit design under test is configured a real or simulated system or circuit, external to the configurable logic system, in which the circuit design under test is intended to operate 2 OPINION AND ORDER environmental timing signal internal clock signal 882 Patent reconfigurable logic device first plurality of reconfigurable logic devices second plurality of reconfigurable logic devices third plurality of reconfigurable logic devices interconnect device time multiplexed interconnection independent clocking circuit design emulation system emulator a timing signal, originating from the environment and received by the logic system, with a frequency that is lower than the internal clock frequency a signal existing within the configurable logic system and invisible to the environment that provides a time base for scheduling the operation of the resynthesized circuit chip that includes a plurality of reconfigurable logic elements and input/output circuitry two or more reconfigurable logic devices, none of which are included in the second plurality of reconfigurable logic devices or the third plurality of reconfigurable logic devices two or more reconfigurable logic devices, none of which are included in the first plurality of reconfigurable logic devices or the third plurality of reconfigurable logic devices two or more reconfigurable logic devices, none of which are included in the first plurality of reconfigurable logic devices or the second plurality of reconfigurable logic devices This term no longer appears in any patent claim at issue. structure capable of receiving data from each reconfigurable logic device in one plurality and transmitting the data to each reconfigurable logic device in another plurality wherein there is no required timing relationship between clock edges 1 a design for an integrated circuit a system capable of reproducing the operation of a circuit design through steps including mapping the circuit design onto hardware a system capable of reproducing the operation of a circuit design through steps including mapping the circuit design onto hardware IT IS SO ORDERED. DATED this 6th day of March, 2014. /s/ Michael W. Mosman MICHAEL W. MOSMAN United States District Judge 1 I remain uncertain as to whether the construction of this term should include further language referring specifically to the structures recited in claims 1 and 5 of the 882 patent. I invite the parties to submit any comments on this question by way of an email to my courtroom deputy clerk before the end of business on Friday, March 14, 2014. 3 OPINION AND ORDER
]]>
Some case metadata and case summaries were written with the help of AI, which can produce inaccuracies. You
should read the full case before relying on it for legal research purposes.
This site is protected by reCAPTCHA and the Google
Privacy Policy and
Terms of Service apply.
